sam3n: change flash io defines according to at91 port style: _OFF for offsets and...

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4417 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c
index fef0f1259e4164d62a5a1db467e627a06ff608dd..6f69afcbf0af9d877829a5448f3097062e34e876 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c
@@ -92,7 +92,7 @@ void clock_init(void)
        uint32_t timeout;
 
        /* Set 4 wait states for flash access, needed for higher CPU clock rates */
-       EEFC_FMR_R = EEFC_FMR_FWS(3);
+       EEFC_FMR = EEFC_FMR_FWS(3);
 
        // Select external slow clock
        if (!(SUPC_SR_R & SUPC_SR_OSCSEL))

diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h
index 03cca342d223b312afcd2e31e24e194f956bac1d..611e61da5b7ad592a5a0ca3960ef8d27f1b573be 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_flash.h
+++ b/bertos/cpu/cortex-m3/io/sam3_flash.h
@@ -37,26 +37,32 @@
 #define SAM3_FLASH_H
 
 /**
- * EEFC registers.
+ * EEFC base register address.
+ */
+#define EEFC_BASE  0x400E0A00
+
+/**
+ * EFC register offsets.
  */
 /*\{*/
-#define EEFC_FMR_R  (*((reg32_t *)0x400E0A00))  ///< Flash Mode Register
-#define EEFC_FCR_R  (*((reg32_t *)0x400E0A04))  ///< Flash Command Register
-#define EEFC_FSR_R  (*((reg32_t *)0x400E0A08))  ///< Flash Status Register
-#define EEFC_FRR_R  (*((reg32_t *)0x400E0A0C))  ///< Flash Result Register
+#define EEFC_FMR_OFF  0x0   ///< Flash Mode Register
+#define EEFC_FCR_OFF  0x4   ///< Flash Command Register
+#define EEFC_FSR_OFF  0x8   ///< Flash Status Register
+#define EEFC_FRR_OFF  0xC   ///< Flash Result Register
 /*\}*/
 
 /**
- * EFC register addresses.
+ * EEFC registers.
  */
 /*\{*/
-#define EEFC_FMR  0x400E0A00   ///< Flash Mode Register
-#define EEFC_FCR  0x400E0A04   ///< Flash Command Register
-#define EEFC_FSR  0x400E0A08   ///< Flash Status Register
-#define EEFC_FRR  0x400E0A0C   ///< Flash Result Register
+#define EEFC_FMR  (*((reg32_t *)(EEFC_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
+#define EEFC_FCR  (*((reg32_t *)(EEFC_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
+#define EEFC_FSR  (*((reg32_t *)(EEFC_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
+#define EEFC_FRR  (*((reg32_t *)(EEFC_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
 /*\}*/
 
 
+
 /**
  * Defines for bit fields in EEFC_FMR register.
  */