Add stm_adc registry structure. Add other registry defines.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3955 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h
index 109bcbbe071934b80639698dda7a70c6effbd7e6..b884b5265630fce6c8e5f467455f21a58c226f62 100644 (file)
--- a/bertos/cpu/cortex-m3/io/stm32_adc.h
+++ b/bertos/cpu/cortex-m3/io/stm32_adc.h
@@ -131,4 +131,150 @@
 #define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
 #define ADC_FLAG_STRT                              ((uint8_t)0X10)
 
+
+/* ADC ADON mask */\r
+#define CR2_ADON_SET               ((uint32_t)0x00000001)\r
+#define CR2_ADON_RESET             ((uint32_t)0xFFFFFFFE)\r
+\r
+/* ADC DMA mask */\r
+#define CR2_DMA_SET                ((uint16_t)0x0100)\r
+#define CR2_DMA_RESET              ((uint16_t)0xFEFF)\r
+\r
+/* ADC RSTCAL mask */\r
+#define CR2_RSTCAL_SET             ((uint16_t)0x0008)\r
+\r
+/* ADC CAL mask */\r
+#define CR2_CAL_SET                ((uint16_t)0x0004)\r
+\r
+/* ADC SWSTRT mask */\r
+#define CR2_SWSTRT_SET             ((uint32_t)0x00400000)\r
+\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_RESET          ((uint32_t)0xFFFF1FFF)\r
+\r
+/* ADC DISCEN mask */\r
+#define CR1_DISCEN_SET             ((uint32_t)0x00000800)\r
+#define CR1_DISCEN_RESET           ((uint32_t)0xFFFFF7FF)\r
+\r
+/* ADC EXTTRIG mask */\r
+#define CR2_EXTTRIG_SET            ((uint32_t)0x00100000)\r
+#define CR2_EXTTRIG_RESET          ((uint32_t)0xFFEFFFFF)\r
+\r
+/* ADC Software start mask */\r
+#define CR2_EXTTRIG_SWSTRT_SET     ((uint32_t)0x00500000)\r
+#define CR2_EXTTRIG_SWSTRT_RESET   ((uint32_t)0xFFAFFFFF)\r
+\r
+/* ADC JAUTO mask */\r
+#define CR1_JAUTO_SET              ((uint32_t)0x00000400)\r
+#define CR1_JAUTO_RESET            ((uint32_t)0xFFFFFBFF)\r
+\r
+/* ADC JDISCEN mask */\r
+#define CR1_JDISCEN_SET            ((uint32_t)0x00001000)\r
+#define CR1_JDISCEN_RESET          ((uint32_t)0xFFFFEFFF)\r
+\r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_RESET          ((uint32_t)0xFFFF8FFF)\r
+\r
+/* ADC JEXTTRIG mask */\r
+#define CR2_JEXTTRIG_SET           ((uint32_t)0x00008000)\r
+#define CR2_JEXTTRIG_RESET         ((uint32_t)0xFFFF7FFF)\r
+\r
+/* ADC JSWSTRT mask */\r
+#define CR2_JSWSTRT_SET            ((uint32_t)0x00200000)\r
+\r
+/* ADC injected software start mask */\r
+#define CR2_JEXTTRIG_JSWSTRT_SET   ((uint32_t)0x00208000)\r
+#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF)\r
+\r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_RESET            ((uint32_t)0xFFFFFFE0)\r
+\r
+/* ADC SQx mask */\r
+#define SQR3_SQ_MASK                ((uint8_t)0x1F)\r
+#define SQR2_SQ_MASK                ((uint8_t)0x1F)\r
+#define SQR1_SQ_MASK                ((uint8_t)0x1F)
+#define SQR1_SQ_LEN_MASK                       0xF
+#define SQR1_SQ_LEN_SHIFT                       20\r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_SET               ((uint8_t)0x1F)\r
+\r
+/* ADC JL mask */\r
+#define JSQR_JL_RESET              ((uint32_t)0xFFCFFFFF)\r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_SET              ((uint8_t)0x07)\r
+#define SMPR2_SMP_SET              ((uint8_t)0x07)\r
+\r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMODE_RESET          ((uint32_t)0xFF3FFDFF)\r
+\r
+/* ADC TSPD mask */\r
+#define CR2_TSVREFE_SET            ((uint32_t)0x00800000)\r
+#define CR2_TSVREFE_RESET          ((uint32_t)0xFF7FFFFF)\r
+\r
+/* ADC JDRx registers= offset */\r
+#define JDR_OFFSET                 ((uint8_t)0x28)\r
+
+/* ADC CR1 register */
+#define CR1_EOCIE                                      5
+#define CR1_AWDIE                                      6
+#define CR1_JEOCIE                                     7
+#define CR1_SCAN                                       8
+#define CR1_AWDSGL                                     9
+#define CR1_JAUTO                                     10
+#define CR1_DISCEN                                    11
+#define CR1_JDISCEN                                   12
+#define CR1_JAWDEN                                    22
+#define CR1_AWDEN                                     23
+
+/* ADC CR2 register */
+#define CR2_ADON                                       0
+#define CR2_CONT                                       1
+#define CR2_CAL                                        2
+#define CR2_RTSCAL                                     3
+#define CR2_DMA                                        8
+#define CR2_ALIGN                                     11
+#define CR2_JEXTTRIG                                  15
+#define CR2_EXTTRIG                                   20
+#define CR2_JSWSTART                                  21
+#define CR2_SWSTART                                   22
+#define CR2_TSVREFE                                   23
+
+/* ADC status */
+#define SR_AWD                                         0
+#define SR_EOC                                         1
+#define SR_JEOC                                        2
+#define SR_JSTRT                                       3
+#define SR_STRT                                        4
+\r
+/* ADC registers Masks */\r
+#define CR1_ADC_CLEAR_MASK             ((uint32_t)0xFFF0FEFF)\r
+#define CR2_ADC_CLEAR_MASK             ((uint32_t)0xFFF1F7FD)\r
+#define SQR1_CLEAR_MASK            ((uint32_t)0xFF0FFFFF)
+\r
+struct stm32_adc
+{
+       reg32_t SR;
+       reg32_t CR1;
+       reg32_t CR2;
+       reg32_t SMPR1;
+       reg32_t SMPR2;
+       reg32_t JOFR1;
+       reg32_t JOFR2;
+       reg32_t JOFR3;
+       reg32_t JOFR4;
+       reg32_t HTR;
+       reg32_t LTR;
+       reg32_t SQR1;
+       reg32_t SQR2;
+       reg32_t SQR3;
+       reg32_t JSQR;
+       reg32_t JDR1;
+       reg32_t JDR2;
+       reg32_t JDR3;
+       reg32_t JDR4;
+       reg32_t DR;
+};
+
 #endif /* STM32_ADC_H */