Set correct timeout and fix error check routine on keytag module. Version 2.1

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1523 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/app/triface/cfg/cfg_ser.h b/app/triface/cfg/cfg_ser.h
index 55efe30114a06668ad801e280a4b0ef4866a9e57..c474c890e730d7bbc32d8ec61414ccb06eaba4c9 100644 (file)
--- a/app/triface/cfg/cfg_ser.h
+++ b/app/triface/cfg/cfg_ser.h
@@ -94,11 +94,11 @@
 /// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
 #define CONFIG_SPI_CLOCK_PHASE 0
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_TXTIMEOUT    10
+/// Default transmit timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_TXTIMEOUT    0
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
-#define CONFIG_SER_RXTIMEOUT    10
+/// Default receive timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
+#define CONFIG_SER_RXTIMEOUT    0
 
 /// Use RTS/CTS handshake
 #define CONFIG_SER_HWHANDSHAKE   0

diff --git a/app/triface/verstag.h b/app/triface/verstag.h
index 1de061be18bfdd71771a2afb13de05ef33509ff0..0be610afdcfe7676382ffbee235614b867730fe0 100644 (file)
--- a/app/triface/verstag.h
+++ b/app/triface/verstag.h
@@ -51,7 +51,7 @@
 #define APP_COPYRIGHT "Copyright 2006, 2007, 2008, Develer (http://www.develer.com/)"
 
 #define VERS_MAJOR 2
-#define VERS_MINOR 0
+#define VERS_MINOR 1
 #define VERS_REV   0
 #define VERS_LETTER ""