lm3s1968: add generic GPIO configuration subsystem.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3400 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/gpio_lm3s.c b/bertos/cpu/cortex-m3/drv/gpio_lm3s.c
new file mode 100644 (file)
index 0000000..770e55b
--- /dev/null
+++ b/bertos/cpu/cortex-m3/drv/gpio_lm3s.c
@@ -0,0 +1,169 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief LM3S1968 GPIO control interface.
+ *
+ * \author Andrea Righi <arighi@develer.com>
+ */
+
+#include <cfg/compiler.h>
+#include <cfg/debug.h>
+#include "io/lm3s.h"
+#include "gpio_lm3s.h"
+
+/* Write a value to the specified pin(s) */
+void lm3s_gpio_pin_write(uint32_t port, uint8_t pins, uint8_t val)
+{
+       HWREG(port + (GPIO_O_DATA + (pins << 2))) = val;
+}
+
+/**
+ * Configure a GPIO pin
+ *
+ * @port: the base address of the GPIO port
+ * @pins: the bit-packed representation of the pin(s)
+ * @mode: the pin(s) configuration mode
+ * @strength: the output drive strength
+ * @type: the pin(s) type
+ *
+ * Return 0 on success, otherwise a negative value.
+ */
+int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
+               uint32_t mode, uint32_t strength, uint32_t type)
+{
+       /* Set the pin direction and mode */
+       switch (mode)
+       {
+       case GPIO_DIR_MODE_IN:
+               HWREG(port + GPIO_O_DIR)   &= ~pins;
+               HWREG(port + GPIO_O_AFSEL) &= ~pins;
+               break;
+       case GPIO_DIR_MODE_OUT:
+               HWREG(port + GPIO_O_DIR)   |= pins;
+               HWREG(port + GPIO_O_AFSEL) &= ~pins;
+               break;
+       case GPIO_DIR_MODE_HW:
+               HWREG(port + GPIO_O_DIR)   &= ~pins;
+               HWREG(port + GPIO_O_AFSEL) |= pins;
+               break;
+       default:
+               ASSERT(0);
+               return -1;
+       }
+       /* Set the output strength */
+       switch (strength)
+       {
+       case GPIO_STRENGTH_2MA:
+               HWREG(port + GPIO_O_DR2R) |= pins;
+               HWREG(port + GPIO_O_DR4R) &= ~pins;
+               HWREG(port + GPIO_O_DR8R) &= ~pins;
+               HWREG(port + GPIO_O_SLR)  &= ~pins;
+               break;
+       case GPIO_STRENGTH_4MA:
+               HWREG(port + GPIO_O_DR2R) &= ~pins;
+               HWREG(port + GPIO_O_DR4R) |= pins;
+               HWREG(port + GPIO_O_DR8R) &= ~pins;
+               HWREG(port + GPIO_O_SLR)  &= ~pins;
+               break;
+       case GPIO_STRENGTH_8MA:
+               HWREG(port + GPIO_O_DR2R) &= ~pins;
+               HWREG(port + GPIO_O_DR4R) &= ~pins;
+               HWREG(port + GPIO_O_DR8R) |= pins;
+               HWREG(port + GPIO_O_SLR)  &= ~pins;
+               break;
+       case GPIO_STRENGTH_8MA_SC:
+               HWREG(port + GPIO_O_DR2R) &= ~pins;
+               HWREG(port + GPIO_O_DR4R) &= ~pins;
+               HWREG(port + GPIO_O_DR8R) |= pins;
+               HWREG(port + GPIO_O_SLR)  |= pins;
+               break;
+       default:
+               ASSERT(0);
+               return -1;
+       }
+       /* Set the pin type */
+       switch (type)
+       {
+       case GPIO_PIN_TYPE_STD:
+               HWREG(port + GPIO_O_ODR)   &= ~pins;
+               HWREG(port + GPIO_O_PUR)   &= ~pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_STD_WPU:
+               HWREG(port + GPIO_O_ODR)   &= ~pins;
+               HWREG(port + GPIO_O_PUR)   |= pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_STD_WPD:
+               HWREG(port + GPIO_O_ODR)   &= ~pins;
+               HWREG(port + GPIO_O_PUR)   &= ~pins;
+               HWREG(port + GPIO_O_PDR)   |= pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_OD:
+               HWREG(port + GPIO_O_ODR)   |= pins;
+               HWREG(port + GPIO_O_PUR)   &= ~pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_OD_WPU:
+               HWREG(port + GPIO_O_ODR)   |= pins;
+               HWREG(port + GPIO_O_PUR)   |= pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_OD_WPD:
+               HWREG(port + GPIO_O_ODR)   |= pins;
+               HWREG(port + GPIO_O_PUR)   &= pins;
+               HWREG(port + GPIO_O_PDR)   |= pins;
+               HWREG(port + GPIO_O_DEN)   |= pins;
+               HWREG(port + GPIO_O_AMSEL) &= ~pins;
+               break;
+       case GPIO_PIN_TYPE_ANALOG:
+               HWREG(port + GPIO_O_ODR)   &= ~pins;
+               HWREG(port + GPIO_O_PUR)   &= ~pins;
+               HWREG(port + GPIO_O_PDR)   &= ~pins;
+               HWREG(port + GPIO_O_DEN)   &= ~pins;
+               HWREG(port + GPIO_O_AMSEL) |= pins;
+       default:
+               ASSERT(0);
+               return -1;
+       }
+       return 0;
+}

diff --git a/bertos/cpu/cortex-m3/drv/gpio_lm3s.h b/bertos/cpu/cortex-m3/drv/gpio_lm3s.h
new file mode 100644 (file)
index 0000000..70179cf
--- /dev/null
+++ b/bertos/cpu/cortex-m3/drv/gpio_lm3s.h
@@ -0,0 +1,75 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief LM3S1968 GPIO control interface.
+ */
+
+#ifndef GPIO_LM3S_H
+#define GPIO_LM3S_H
+
+/**
+ * GPIO mode
+ */
+/*\{*/
+#define GPIO_DIR_MODE_IN        0x00000000  //< Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT       0x00000001  //< Pin is a GPIO output
+#define GPIO_DIR_MODE_HW        0x00000002  //< Pin is a peripheral function
+/*\}*/
+
+/**
+ * GPIO strenght
+ */
+/*\{*/
+#define GPIO_STRENGTH_2MA       0x00000001  //< 2mA drive strength
+#define GPIO_STRENGTH_4MA       0x00000002  //< 4mA drive strength
+#define GPIO_STRENGTH_8MA       0x00000004  //< 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC    0x0000000C  //< 8mA drive with slew rate control
+/*\}*/
+
+/**
+ * GPIO type
+ */
+/*\{*/
+#define GPIO_PIN_TYPE_STD       0x00000008  //< Push-pull
+#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  //< Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  //< Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD        0x00000009  //< Open-drain
+#define GPIO_PIN_TYPE_OD_WPU    0x0000000B  //< Open-drain with weak pull-up
+#define GPIO_PIN_TYPE_OD_WPD    0x0000000D  //< Open-drain with weak pull-down
+#define GPIO_PIN_TYPE_ANALOG    0x00000000  //< Analog comparator
+/*\}*/
+
+int lm3s_gpio_pin_config(uint32_t port, uint8_t pins,
+               uint32_t mode, uint32_t strength, uint32_t type);
+void lm3s_gpio_pin_write(uint32_t port, uint8_t pins, uint8_t val);
+
+#endif /* GPIO_LM3S_H */

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index 7bcfc9ba084bf297110ca4f9f93d60d851501ed3..a0c7209f2f45176e3e267d64a9cdb69ae42c560d 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -40,6 +40,7 @@
 #include "clock_lm3s.h" /* __delay() */
 #include "cfg/cfg_debug.h"
 #include "io/lm3s.h"
+#include "gpio_lm3s.h"
 
 INLINE void uart_disable(size_t base)
 {
@@ -125,14 +126,9 @@ INLINE void kdbg_hw_init(void)
        SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
        SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
        __delay(512);
-
        /* Set GPIO A0 and A1 as UART pins */
-       HWREG(GPIO_PORTA_BASE + GPIO_O_DIR) |= BV(0) | BV(1);
-       HWREG(GPIO_PORTA_BASE + GPIO_O_AFSEL) |= BV(0) | BV(1);
-       HWREG(GPIO_PORTA_BASE + GPIO_O_DR2R) |= BV(0) | BV(1);
-       HWREG(GPIO_PORTA_BASE + GPIO_O_DEN) |= BV(0) | BV(1);
-       HWREG(GPIO_PORTA_BASE + GPIO_O_AMSEL) &= ~(BV(0) | BV(1));
-
+       lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(0) | BV(1),
+                       GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
        /* 115.200, 8-bit word, no parity, one stop bit */
        uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);
 }

diff --git a/bertos/cpu/cortex-m3/drv/ssi_lm3s.h b/bertos/cpu/cortex-m3/drv/ssi_lm3s.h
index 69b88ac2abe540a73c36657fc2d9ef7cc561de6b..901f62885bb6e06bc8059df0c97123d6c23d7cf7 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/ssi_lm3s.h
+++ b/bertos/cpu/cortex-m3/drv/ssi_lm3s.h
@@ -75,4 +75,4 @@ INLINE void lm3s_ssi_wait_txdone(uint32_t base)
                cpu_relax();
 }
 
-#endif /* LM3S_SSI_H */
+#endif /* SSI_LM3S_H */