#include <cpu/detect.h>
#include <cfg/compiler.h>
-#if CPU_CM3_AT91SAM3N
- /*
- * Redefine CPU detect macros for compatibility with stock
- * Atmel IO include file.
- */
- #if CPU_CM3_AT91SAM3N4
- #define sam3n4
- #elif CPU_CM3_AT91SAM3N2
- #define sam3n2
- #elif CPU_CM3_AT91SAM3N1
- #define sam3n1
- #endif
- #include "sam3n.h"
-#else
- #error Unimplemented CPU
-#endif
+/*
+ * Peripherals IDs, same as interrupt numbers.
+ */
+#define SUPC_ID INT_SUPC ///< Supply Controller (SUPC)
+#define RSTC_ID INT_RSTC ///< Reset Controller (RSTC)
+#define RTC_ID INT_RTC ///< Real Time Clock (RTC)
+#define RTT_ID INT_RTT ///< Real Time Timer (RTT)
+#define WDT_ID INT_WDT ///< Watchdog Timer (WDT)
+#define PMC_ID INT_PMC ///< Power Management Controller (PMC)
+#define EFC_ID INT_EFC ///< Enhanced Flash Controller (EFC)
+#define UART0_ID INT_UART0 ///< UART 0 (UART0)
+#define UART1_ID INT_UART1 ///< UART 1 (UART1)
+#define UART2_ID INT_UART2 ///< UART 0 (UART0)
+#define UART3_ID INT_UART3 ///< UART 1 (UART1)
+#define PIOA_ID INT_PIOA ///< Parallel I/O Controller A (PIOA)
+#define PIOB_ID INT_PIOB ///< Parallel I/O Controller B (PIOB)
+#define PIOC_ID INT_PIOC ///< Parallel I/O Controller C (PIOC)
+#define US0_ID INT_USART0 ///< USART 0 (USART0)
+#define US1_ID INT_USART1 ///< USART 1 (USART1)
+#define TWI0_ID INT_TWI0 ///< Two Wire Interface 0 (TWI0)
+#define TWI1_ID INT_TWI1 ///< Two Wire Interface 1 (TWI1)
+#define SPI0_ID INT_SPI ///< Serial Peripheral Interface (SPI)
+#define TC0_ID INT_TC0 ///< Timer/Counter 0 (TC0)
+#define TC1_ID INT_TC1 ///< Timer/Counter 1 (TC1)
+#define TC2_ID INT_TC2 ///< Timer/Counter 2 (TC2)
+#define TC3_ID INT_TC3 ///< Timer/Counter 3 (TC3)
+#define TC4_ID INT_TC4 ///< Timer/Counter 4 (TC4)
+#define TC5_ID INT_TC5 ///< Timer/Counter 5 (TC5)
+#define ADC_ID INT_ADC ///< Analog To Digital Converter (ADC)
+#define DACC_ID INT_DACC ///< Digital To Analog Converter (DACC)
+#define PWM_ID INT_PWM ///< Pulse Width Modulation (PWM)
+
+/*
+ * Hardware features for drivers.
+ */
+#define USART_HAS_PDC 1
+
+#include "sam3_sysctl.h"
+#include "sam3_pmc.h"
+#include "sam3_memmap.h"
+#include "sam3_ints.h"
+#include "sam3_pio.h"
#include "sam3_nvic.h"
+#include "sam3_uart.h"
+#include "sam3_us.h"
+#include "sam3_spi.h"
+#include "sam3_flash.h"
+#include "sam3_wdt.h"
/**
- * Total number of interrupts.
+ * UART I/O pins
*/
/*\{*/
-#define NUM_INTERRUPTS 32
+#if CPU_CM3_AT91SAM3U
+ #define RXD0 11
+ #define TXD0 12
+#else
+ #define RXD0 9
+ #define TXD0 10
+ #define RXD1 2
+ #define TXD1 3
+#endif
/*\}*/
/**
- * UART PIO pins
+ * PIO I/O pins
*/
/*\{*/
-#ifdef CPU_CM3_AT91SAM3U
- #define GPIO_UART0_RX_PIN BV(11)
- #define GPIO_UART0_TX_PIN BV(12)
+#if CPU_CM3_AT91SAM3U
+ #define SPI0_SPCK 15
+ #define SPI0_MOSI 14
+ #define SPI0_MISO 13
#else
- #define GPIO_UART0_RX_PIN BV(9)
- #define GPIO_UART0_TX_PIN BV(10)
- #define GPIO_UART1_RX_PIN BV(2)
- #define GPIO_UART1_TX_PIN BV(3)
+ #define SPI0_SPCK 14
+ #define SPI0_MOSI 13
+ #define SPI0_MISO 12
#endif
/*\}*/
-
#endif /* SAM3_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief ATSAM3 enhanced embedded flash controller definitions.
+ */
+
+#ifndef SAM3_FLASH_H
+#define SAM3_FLASH_H
+
+/**
+ * EEFC base register address.
+ */
+#define EEFC_BASE 0x400E0A00
+
+/**
+ * EFC register offsets.
+ */
+/*\{*/
+#define EEFC_FMR_OFF 0x0 ///< Flash Mode Register
+#define EEFC_FCR_OFF 0x4 ///< Flash Command Register
+#define EEFC_FSR_OFF 0x8 ///< Flash Status Register
+#define EEFC_FRR_OFF 0xC ///< Flash Result Register
+/*\}*/
+
+/**
+ * EEFC registers.
+ */
+/*\{*/
+#define EEFC_FMR (*((reg32_t *)(EEFC_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
+#define EEFC_FCR (*((reg32_t *)(EEFC_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
+#define EEFC_FSR (*((reg32_t *)(EEFC_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
+#define EEFC_FRR (*((reg32_t *)(EEFC_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
+/*\}*/
+
+
+
+/**
+ * Defines for bit fields in EEFC_FMR register.
+ */
+/*\{*/
+#define EEFC_FMR_FRDY 0 ///< Ready Interrupt Enable
+#define EEFC_FMR_FWS_SHIFT 8
+#define EEFC_FMR_FWS_MASK (0xf << EEFC_FMR_FWS_SHIFT) ///< Flash Wait State
+#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_MASK & ((value) << EEFC_FMR_FWS_SHIFT))
+#define EEFC_FMR_FAM 24 ///< Flash Access Mode
+/*\}*/
+
+/**
+ * Defines for bit fields in EEFC_FCR register.
+ */
+/*\{*/
+#define EEFC_FCR_FCMD_MASK 0xff ///< Flash Command
+#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_MASK & (value))
+#define EEFC_FCR_FARG_SHIFT 8
+#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) ///< Flash Command Argument
+#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT))
+#define EEFC_FCR_FKEY_SHIFT 24
+#define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT) ///< Flash Writing Protection Key
+#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_MASK & ((value) << EEFC_FCR_FKEY_SHIFT))
+/*\}*/
+
+/**
+ * Defines for bit fields in EEFC_FSR register.
+ */
+/*\{*/
+#define EEFC_FSR_FRDY 0 ///< Flash Ready Status
+#define EEFC_FSR_FCMDE 1 ///< Flash Command Error Status
+#define EEFC_FSR_FLOCKE 2 ///< Flash Lock Error Status
+/*\}*/
+
+#endif /* SAM3_FLASH_H */
*
* -->
*
- * \brief AT91SAM3 NVIC hardware.
+ * \brief ATSAM3 NVIC hardware.
+ *
+ * This file does not follow the BeRTOS AT91 register naming convention,
+ * because the NVIC subsystem is in common with other Cortex-M3 ports.
+ * Take care when using bit definition macros, they don't define bit numbers
+ * but values, i.e. you must not use BV(). Moreover register names have
+ * the _R suffix and offsets don't have the _OFF one.
+ * Someday we will fix this incoherence...
*/
#ifndef SAM3_NVIC_H
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2007,2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ *
+ * \author Francesco Sacchi <batt@develer.com>
+ *
+ * ATSAM3 Parallel input/output controller.
+ * This file is based on NUT/OS implementation. See license below.
+ */
+
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+#ifndef SAM3_PIO_H
+#define SAM3_PIO_H
+
+/**
+ * PIO registers base addresses.
+ */
+/*\{*/
+#define PIOA_BASE 0x400E0E00
+#define PIOB_BASE 0x400E1000
+#define PIOC_BASE 0x400E1200
+/*\}*/
+
+/** PIO Register Offsets */
+/*\{*/
+#define PIO_PER_OFF 0x00000000 ///< PIO enable register offset.
+#define PIO_PDR_OFF 0x00000004 ///< PIO disable register offset.
+#define PIO_PSR_OFF 0x00000008 ///< PIO status register offset.
+#define PIO_OER_OFF 0x00000010 ///< Output enable register offset.
+#define PIO_ODR_OFF 0x00000014 ///< Output disable register offset.
+#define PIO_OSR_OFF 0x00000018 ///< Output status register offset.
+#define PIO_IFER_OFF 0x00000020 ///< Input filter enable register offset.
+#define PIO_IFDR_OFF 0x00000024 ///< Input filter disable register offset.
+#define PIO_IFSR_OFF 0x00000028 ///< Input filter status register offset.
+#define PIO_SODR_OFF 0x00000030 ///< Set output data register offset.
+#define PIO_CODR_OFF 0x00000034 ///< Clear output data register offset.
+#define PIO_ODSR_OFF 0x00000038 ///< Output data status register offset.
+#define PIO_PDSR_OFF 0x0000003C ///< Pin data status register offset.
+#define PIO_IER_OFF 0x00000040 ///< Interrupt enable register offset.
+#define PIO_IDR_OFF 0x00000044 ///< Interrupt disable register offset.
+#define PIO_IMR_OFF 0x00000048 ///< Interrupt mask register offset.
+#define PIO_ISR_OFF 0x0000004C ///< Interrupt status register offset.
+#define PIO_MDER_OFF 0x00000050 ///< Multi-driver enable register offset.
+#define PIO_MDDR_OFF 0x00000054 ///< Multi-driver disable register offset.
+#define PIO_MDSR_OFF 0x00000058 ///< Multi-driver status register offset.
+#define PIO_PUDR_OFF 0x00000060 ///< Pull-up disable register offset.
+#define PIO_PUER_OFF 0x00000064 ///< Pull-up enable register offset.
+#define PIO_PUSR_OFF 0x00000068 ///< Pull-up status register offset.
+#define PIO_ABCDSR1_OFF 0x00000070 ///< PIO peripheral select register 1 offset.
+#define PIO_ABCDSR2_OFF 0x00000074 ///< PIO peripheral select register 2 offset.
+#define PIO_OWER_OFF 0x000000A0 ///< PIO output write enable register offset.
+#define PIO_OWDR_OFF 0x000000A4 ///< PIO output write disable register offset.
+#define PIO_OWSR_OFF 0x000000A8 ///< PIO output write status register offset.
+/*\}*/
+
+/** Single PIO Register Addresses */
+/*\{*/
+#if defined(PIO_BASE)
+ #define PIO_ACCESS(offset) (*((reg32_t *)(PIO_BASE + (offset))))
+
+ #define PIO_PER PIO_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
+ #define PIO_PDR PIO_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
+ #define PIO_PSR PIO_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
+ #define PIO_OER PIO_ACCESS(PIO_OER_OFF) ///< Output enable register address.
+ #define PIO_ODR PIO_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
+ #define PIO_OSR PIO_ACCESS(PIO_OSR_OFF) ///< Output status register address.
+ #define PIO_IFER PIO_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
+ #define PIO_IFDR PIO_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
+ #define PIO_IFSR PIO_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
+ #define PIO_SODR PIO_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
+ #define PIO_CODR PIO_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
+ #define PIO_ODSR PIO_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
+ #define PIO_PDSR PIO_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
+ #define PIO_IER PIO_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
+ #define PIO_IDR PIO_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
+ #define PIO_IMR PIO_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
+ #define PIO_ISR PIO_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
+ #define PIO_MDER PIO_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
+ #define PIO_MDDR PIO_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
+ #define PIO_MDSR PIO_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
+ #define PIO_PUDR PIO_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
+ #define PIO_PUER PIO_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
+ #define PIO_PUSR PIO_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
+ #define PIO_ABCDSR1 PIO_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
+ #define PIO_ABCDSR2 PIO_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
+ #define PIO_OWER PIO_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
+ #define PIO_OWDR PIO_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
+ #define PIO_OWSR PIO_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
+#endif /* PIO_BASE */
+/*\}*/
+
+/** PIO A Register Addresses */
+/*\{*/
+#if defined(PIOA_BASE)
+ #define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset))))
+
+ #define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
+ #define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
+ #define PIOA_PSR PIOA_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
+ #define PIOA_OER PIOA_ACCESS(PIO_OER_OFF) ///< Output enable register address.
+ #define PIOA_ODR PIOA_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
+ #define PIOA_OSR PIOA_ACCESS(PIO_OSR_OFF) ///< Output status register address.
+ #define PIOA_IFER PIOA_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
+ #define PIOA_IFDR PIOA_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
+ #define PIOA_IFSR PIOA_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
+ #define PIOA_SODR PIOA_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
+ #define PIOA_CODR PIOA_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
+ #define PIOA_ODSR PIOA_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
+ #define PIOA_PDSR PIOA_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
+ #define PIOA_IER PIOA_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
+ #define PIOA_IDR PIOA_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
+ #define PIOA_IMR PIOA_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
+ #define PIOA_ISR PIOA_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
+ #define PIOA_MDER PIOA_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
+ #define PIOA_MDDR PIOA_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
+ #define PIOA_MDSR PIOA_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
+ #define PIOA_PUDR PIOA_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
+ #define PIOA_PUER PIOA_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
+ #define PIOA_PUSR PIOA_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
+ #define PIOA_ABCDSR1 PIOA_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
+ #define PIOA_ABCDSR2 PIOA_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 2 address.
+ #define PIOA_OWER PIOA_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
+ #define PIOA_OWDR PIOA_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
+ #define PIOA_OWSR PIOA_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
+#endif /* PIOA_BASE */
+/*\}*/
+
+/** PIO B Register Addresses */
+/*\{*/
+#if defined(PIOB_BASE)
+ #define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset))))
+
+ #define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
+ #define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
+ #define PIOB_PSR PIOB_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
+ #define PIOB_OER PIOB_ACCESS(PIO_OER_OFF) ///< Output enable register address.
+ #define PIOB_ODR PIOB_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
+ #define PIOB_OSR PIOB_ACCESS(PIO_OSR_OFF) ///< Output status register address.
+ #define PIOB_IFER PIOB_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
+ #define PIOB_IFDR PIOB_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
+ #define PIOB_IFSR PIOB_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
+ #define PIOB_SODR PIOB_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
+ #define PIOB_CODR PIOB_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
+ #define PIOB_ODSR PIOB_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
+ #define PIOB_PDSR PIOB_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
+ #define PIOB_IER PIOB_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
+ #define PIOB_IDR PIOB_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
+ #define PIOB_IMR PIOB_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
+ #define PIOB_ISR PIOB_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
+ #define PIOB_MDER PIOB_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
+ #define PIOB_MDDR PIOB_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
+ #define PIOB_MDSR PIOB_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
+ #define PIOB_PUDR PIOB_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
+ #define PIOB_PUER PIOB_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
+ #define PIOB_PUSR PIOB_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
+ #define PIOB_ABCDSR1 PIOB_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
+ #define PIOB_ABCDSR2 PIOB_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 2 address.
+ #define PIOB_OWER PIOB_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
+ #define PIOB_OWDR PIOB_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
+ #define PIOB_OWSR PIOB_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
+#endif /* PIOB_BASE */
+/*\}*/
+
+/** PIO C Register Addresses */
+/*\{*/
+#if defined(PIOC_BASE)
+ #define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset))))
+
+ #define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
+ #define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
+ #define PIOC_PSR PIOC_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
+ #define PIOC_OER PIOC_ACCESS(PIO_OER_OFF) ///< Output enable register address.
+ #define PIOC_ODR PIOC_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
+ #define PIOC_OSR PIOC_ACCESS(PIO_OSR_OFF) ///< Output status register address.
+ #define PIOC_IFER PIOC_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
+ #define PIOC_IFDR PIOC_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
+ #define PIOC_IFSR PIOC_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
+ #define PIOC_SODR PIOC_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
+ #define PIOC_CODR PIOC_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
+ #define PIOC_ODSR PIOC_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
+ #define PIOC_PDSR PIOC_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
+ #define PIOC_IER PIOC_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
+ #define PIOC_IDR PIOC_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
+ #define PIOC_IMR PIOC_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
+ #define PIOC_ISR PIOC_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
+ #define PIOC_MDER PIOC_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
+ #define PIOC_MDDR PIOC_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
+ #define PIOC_MDSR PIOC_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
+ #define PIOC_PUDR PIOC_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
+ #define PIOC_PUER PIOC_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
+ #define PIOC_PUSR PIOC_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
+ #define PIOC_ABCDSR1 PIOC_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
+ #define PIOC_ABCDSR2 PIOC_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 2 address.
+ #define PIOC_OWER PIOC_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
+ #define PIOC_OWDR PIOC_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
+ #define PIOC_OWSR PIOC_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
+#endif /* PIOC_BASE */
+/*\}*/
+
+#endif /* SAM3_PIO_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief AT91SAM3 PMC hardware.
+ */
+
+#ifndef SAM3_PMC_H
+#define SAM3_PMC_H
+
+/** PMC registers base. */
+#define PMC_BASE 0x400E0400
+
+/**
+ * PMC register offsets.
+ */
+/*\{*/
+#define PMC_SCER_OFF 0x00 ///< System Clock Enable Register
+#define PMC_SCDR_OFF 0x04 ///< System Clock Disable Register
+#define PMC_SCSR_OFF 0x08 ///< System Clock Status Register
+#define PMC_PCER_OFF 0x10 ///< Peripheral Clock Enable Register
+#define PMC_PCDR_OFF 0x14 ///< Peripheral Clock Disable Register
+#define PMC_PCSR_OFF 0x18 ///< Peripheral Clock Status Register
+#define PMC_MOR_OFF 0x20 ///< Main Oscillator Register
+#define PMC_MCFR_OFF 0x24 ///< Main Clock Frequency Register
+#define PMC_PLLR_OFF 0x28 ///< PLL Register
+#define PMC_MCKR_OFF 0x30 ///< Master Clock Register
+#define PMC_PCK_OFF 0x40 ///< Programmable Clock 0 Register
+#define PMC_IER_OFF 0x60 ///< Interrupt Enable Register
+#define PMC_IDR_OFF 0x64 ///< Interrupt Disable Register
+#define PMC_SR_OFF 0x68 ///< Status Register
+#define PMC_IMR_OFF 0x6C ///< Interrupt Mask Register
+#define PMC_FSMR_OFF 0x70 ///< Fast Startup Mode Register
+#define PMC_FSPR_OFF 0x74 ///< Fast Startup Polarity Register
+#define PMC_FOCR_OFF 0x78 ///< Fault Output Clear Register
+#define PMC_WPMR_OFF 0xE4 ///< Write Protect Mode Register
+#define PMC_WPSR_OFF 0xE8 ///< Write Protect Status Register
+#define PMC_OCR_OFF 0x110 ///< Oscillator Calibration Register
+/*\}*/
+
+/**
+ * PMC registers.
+ */
+/*\{*/
+#define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System Clock Enable Register
+#define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System Clock Disable Register
+#define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System Clock Status Register
+#define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral Clock Enable Register
+#define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral Clock Disable Register
+#define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral Clock Status Register
+#define CKGR_MOR (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF ))) ///< Main Oscillator Register
+#define CKGR_MCFR (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF))) ///< Main Clock Frequency Register
+#define CKGR_PLLR (*((reg32_t *)(PMC_BASE + PMC_PLLR_OFF))) ///< PLL Register
+#define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master Clock Register
+#define PMC_PCK (*((reg32_t *)(PMC_BASE + PMC_PCK_OFF ))) ///< Programmable Clock 0 Register
+#define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF ))) ///< Interrupt Enable Register
+#define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF ))) ///< Interrupt Disable Register
+#define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF ))) ///< Status Register
+#define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF ))) ///< Interrupt Mask Register
+#define PMC_FSMR (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF))) ///< Fast Startup Mode Register
+#define PMC_FSPR (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF))) ///< Fast Startup Polarity Register
+#define PMC_FOCR (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF))) ///< Fault Output Clear Register
+#define PMC_WPMR (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF))) ///< Write Protect Mode Register
+#define PMC_WPSR (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF))) ///< Write Protect Status Register
+#define PMC_OCR (*((reg32_t *)(PMC_BASE + PMC_OCR_OFF ))) ///< Oscillator Calibration Register
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_SCER register.
+ */
+/*\{*/
+#define PMC_SCER_PCK0 8 ///< Programmable Clock 0 Output Enable
+#define PMC_SCER_PCK1 9 ///< Programmable Clock 1 Output Enable
+#define PMC_SCER_PCK2 10 ///< Programmable Clock 2 Output Enable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_SCDR register.
+ */
+/*\{*/
+#define PMC_SCDR_PCK0 8 ///< Programmable Clock 0 Output Disable
+#define PMC_SCDR_PCK1 9 ///< Programmable Clock 1 Output Disable
+#define PMC_SCDR_PCK2 10 ///< Programmable Clock 2 Output Disable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_SCSR register.
+ */
+/*\{*/
+#define PMC_SCSR_PCK0 8 ///< Programmable Clock 0 Output Status
+#define PMC_SCSR_PCK1 9 ///< Programmable Clock 1 Output Status
+#define PMC_SCSR_PCK2 10 ///< Programmable Clock 2 Output Status
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_PCER register.
+ */
+/*\{*/
+#define PMC_PCER_PID2 2 ///< Peripheral Clock 2 Enable
+#define PMC_PCER_PID3 3 ///< Peripheral Clock 3 Enable
+#define PMC_PCER_PID4 4 ///< Peripheral Clock 4 Enable
+#define PMC_PCER_PID5 5 ///< Peripheral Clock 5 Enable
+#define PMC_PCER_PID6 6 ///< Peripheral Clock 6 Enable
+#define PMC_PCER_PID7 7 ///< Peripheral Clock 7 Enable
+#define PMC_PCER_PID8 8 ///< Peripheral Clock 8 Enable
+#define PMC_PCER_PID9 9 ///< Peripheral Clock 9 Enable
+#define PMC_PCER_PID10 10 ///< Peripheral Clock 10 Enable
+#define PMC_PCER_PID11 11 ///< Peripheral Clock 11 Enable
+#define PMC_PCER_PID12 12 ///< Peripheral Clock 12 Enable
+#define PMC_PCER_PID13 13 ///< Peripheral Clock 13 Enable
+#define PMC_PCER_PID14 14 ///< Peripheral Clock 14 Enable
+#define PMC_PCER_PID15 15 ///< Peripheral Clock 15 Enable
+#define PMC_PCER_PID16 16 ///< Peripheral Clock 16 Enable
+#define PMC_PCER_PID17 17 ///< Peripheral Clock 17 Enable
+#define PMC_PCER_PID18 18 ///< Peripheral Clock 18 Enable
+#define PMC_PCER_PID19 19 ///< Peripheral Clock 19 Enable
+#define PMC_PCER_PID20 20 ///< Peripheral Clock 20 Enable
+#define PMC_PCER_PID21 21 ///< Peripheral Clock 21 Enable
+#define PMC_PCER_PID22 22 ///< Peripheral Clock 22 Enable
+#define PMC_PCER_PID23 23 ///< Peripheral Clock 23 Enable
+#define PMC_PCER_PID24 24 ///< Peripheral Clock 24 Enable
+#define PMC_PCER_PID25 25 ///< Peripheral Clock 25 Enable
+#define PMC_PCER_PID26 26 ///< Peripheral Clock 26 Enable
+#define PMC_PCER_PID27 27 ///< Peripheral Clock 27 Enable
+#define PMC_PCER_PID28 28 ///< Peripheral Clock 28 Enable
+#define PMC_PCER_PID29 29 ///< Peripheral Clock 29 Enable
+#define PMC_PCER_PID30 30 ///< Peripheral Clock 30 Enable
+#define PMC_PCER_PID31 31 ///< Peripheral Clock 31 Enable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_PCDR register.
+ */
+/*\{*/
+#define PMC_PCDR_PID2 2 ///< Peripheral Clock 2 Disable
+#define PMC_PCDR_PID3 3 ///< Peripheral Clock 3 Disable
+#define PMC_PCDR_PID4 4 ///< Peripheral Clock 4 Disable
+#define PMC_PCDR_PID5 5 ///< Peripheral Clock 5 Disable
+#define PMC_PCDR_PID6 6 ///< Peripheral Clock 6 Disable
+#define PMC_PCDR_PID7 7 ///< Peripheral Clock 7 Disable
+#define PMC_PCDR_PID8 8 ///< Peripheral Clock 8 Disable
+#define PMC_PCDR_PID9 9 ///< Peripheral Clock 9 Disable
+#define PMC_PCDR_PID10 10 ///< Peripheral Clock 10 Disable
+#define PMC_PCDR_PID11 11 ///< Peripheral Clock 11 Disable
+#define PMC_PCDR_PID12 12 ///< Peripheral Clock 12 Disable
+#define PMC_PCDR_PID13 13 ///< Peripheral Clock 13 Disable
+#define PMC_PCDR_PID14 14 ///< Peripheral Clock 14 Disable
+#define PMC_PCDR_PID15 15 ///< Peripheral Clock 15 Disable
+#define PMC_PCDR_PID16 16 ///< Peripheral Clock 16 Disable
+#define PMC_PCDR_PID17 17 ///< Peripheral Clock 17 Disable
+#define PMC_PCDR_PID18 18 ///< Peripheral Clock 18 Disable
+#define PMC_PCDR_PID19 19 ///< Peripheral Clock 19 Disable
+#define PMC_PCDR_PID20 20 ///< Peripheral Clock 20 Disable
+#define PMC_PCDR_PID21 21 ///< Peripheral Clock 21 Disable
+#define PMC_PCDR_PID22 22 ///< Peripheral Clock 22 Disable
+#define PMC_PCDR_PID23 23 ///< Peripheral Clock 23 Disable
+#define PMC_PCDR_PID24 24 ///< Peripheral Clock 24 Disable
+#define PMC_PCDR_PID25 25 ///< Peripheral Clock 25 Disable
+#define PMC_PCDR_PID26 26 ///< Peripheral Clock 26 Disable
+#define PMC_PCDR_PID27 27 ///< Peripheral Clock 27 Disable
+#define PMC_PCDR_PID28 28 ///< Peripheral Clock 28 Disable
+#define PMC_PCDR_PID29 29 ///< Peripheral Clock 29 Disable
+#define PMC_PCDR_PID30 30 ///< Peripheral Clock 30 Disable
+#define PMC_PCDR_PID31 31 ///< Peripheral Clock 31 Disable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_PCSR register.
+ */
+/*\{*/
+#define PMC_PCSR_PID2 2 ///< Peripheral Clock 2 Status
+#define PMC_PCSR_PID3 3 ///< Peripheral Clock 3 Status
+#define PMC_PCSR_PID4 4 ///< Peripheral Clock 4 Status
+#define PMC_PCSR_PID5 5 ///< Peripheral Clock 5 Status
+#define PMC_PCSR_PID6 6 ///< Peripheral Clock 6 Status
+#define PMC_PCSR_PID7 7 ///< Peripheral Clock 7 Status
+#define PMC_PCSR_PID8 8 ///< Peripheral Clock 8 Status
+#define PMC_PCSR_PID9 9 ///< Peripheral Clock 9 Status
+#define PMC_PCSR_PID10 10 ///< Peripheral Clock 10 Status
+#define PMC_PCSR_PID11 11 ///< Peripheral Clock 11 Status
+#define PMC_PCSR_PID12 12 ///< Peripheral Clock 12 Status
+#define PMC_PCSR_PID13 13 ///< Peripheral Clock 13 Status
+#define PMC_PCSR_PID14 14 ///< Peripheral Clock 14 Status
+#define PMC_PCSR_PID15 15 ///< Peripheral Clock 15 Status
+#define PMC_PCSR_PID16 16 ///< Peripheral Clock 16 Status
+#define PMC_PCSR_PID17 17 ///< Peripheral Clock 17 Status
+#define PMC_PCSR_PID18 18 ///< Peripheral Clock 18 Status
+#define PMC_PCSR_PID19 19 ///< Peripheral Clock 19 Status
+#define PMC_PCSR_PID20 20 ///< Peripheral Clock 20 Status
+#define PMC_PCSR_PID21 21 ///< Peripheral Clock 21 Status
+#define PMC_PCSR_PID22 22 ///< Peripheral Clock 22 Status
+#define PMC_PCSR_PID23 23 ///< Peripheral Clock 23 Status
+#define PMC_PCSR_PID24 24 ///< Peripheral Clock 24 Status
+#define PMC_PCSR_PID25 25 ///< Peripheral Clock 25 Status
+#define PMC_PCSR_PID26 26 ///< Peripheral Clock 26 Status
+#define PMC_PCSR_PID27 27 ///< Peripheral Clock 27 Status
+#define PMC_PCSR_PID28 28 ///< Peripheral Clock 28 Status
+#define PMC_PCSR_PID29 29 ///< Peripheral Clock 29 Status
+#define PMC_PCSR_PID30 30 ///< Peripheral Clock 30 Status
+#define PMC_PCSR_PID31 31 ///< Peripheral Clock 31 Status
+/*\}*/
+
+/**
+ * Defines for bit fields in CKGR_MOR register.
+ */
+/*\{*/
+#define CKGR_MOR_MOSCXTEN 0 ///< Main Crystal Oscillator Enable
+#define CKGR_MOR_MOSCXTBY 1 ///< Main Crystal Oscillator Bypass
+#define CKGR_MOR_WAITMODE 2 ///< Wait Mode Command
+#define CKGR_MOR_MOSCRCEN 3 ///< Main On-Chip RC Oscillator Enable
+#define CKGR_MOR_MOSCRCF_SHIFT 4
+#define CKGR_MOR_MOSCRCF_MASK (0x7 << CKGR_MOR_MOSCRCF_SHIFT) ///< Main On-Chip RC Oscillator Frequency Selection
+#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
+#define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCXTST_SHIFT 8
+#define CKGR_MOR_MOSCXTST_MASK (0xff << CKGR_MOR_MOSCXTST_SHIFT) ///< Main Crystal Oscillator Start-up Time
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
+#define CKGR_MOR_KEY_SHIFT 16
+#define CKGR_MOR_KEY_MASK (0xffu << CKGR_MOR_KEY_SHIFT) ///< Password
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))
+#define CKGR_MOR_MOSCSEL 24 ///< Main Oscillator Selection
+#define CKGR_MOR_CFDEN 25 ///< Clock Failure Detector Enable
+/*\}*/
+
+/**
+ * Defines for bit fields in CKGR_MCFR register.
+ */
+/*\{*/
+#define CKGR_MCFR_MAINF_MASK 0xffff ///< Main Clock Frequency mask
+#define CKGR_MCFR_MAINFRDY 16 ///< Main Clock Ready
+/*\}*/
+
+/**
+ * Defines for bit fields in CKGR_PLLR register.
+ */
+/*\{*/
+#define CKGR_PLLR_DIV_MASK 0xff ///< Divider mask
+#define CKGR_PLLR_DIV(value) (CKGR_PLLR_DIV_MASK & (value))
+#define CKGR_PLLR_PLLCOUNT_SHIFT 8
+#define CKGR_PLLR_PLLCOUNT_MASK (0x3f << CKGR_PLLR_PLLCOUNT_SHIFT) ///< PLL Counter mask
+#define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))
+#define CKGR_PLLR_MUL_SHIFT 16
+#define CKGR_PLLR_MUL_MASK (0x7ff << CKGR_PLLR_MUL_SHIFT) ///< PLL Multiplier mask
+#define CKGR_PLLR_MUL(value) (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))
+#define CKGR_PLLR_STUCKTO1 29
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_MCKR register.
+ */
+/*\{*/
+#define PMC_MCKR_CSS_MASK 0x3 ///< Master Clock Source Selection mask
+#define PMC_MCKR_CSS_SLOW_CLK 0x0 ///< Slow Clock is selected
+#define PMC_MCKR_CSS_MAIN_CLK 0x1 ///< Main Clock is selected
+#define PMC_MCKR_CSS_PLL_CLK 0x2 ///< PLL Clock is selected
+#define PMC_MCKR_PRES_SHIFT 4
+#define PMC_MCKR_PRES_MASK (0x7 << PMC_MCKR_PRES_SHIFT) ///< Processor Clock Prescaler mask
+#define PMC_MCKR_PRES_CLK (0x0 << PMC_MCKR_PRES_SHIFT) ///< Selected clock
+#define PMC_MCKR_PRES_CLK_2 (0x1 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 2
+#define PMC_MCKR_PRES_CLK_4 (0x2 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 4
+#define PMC_MCKR_PRES_CLK_8 (0x3 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 8
+#define PMC_MCKR_PRES_CLK_16 (0x4 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 16
+#define PMC_MCKR_PRES_CLK_32 (0x5 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 32
+#define PMC_MCKR_PRES_CLK_64 (0x6 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 64
+#define PMC_MCKR_PRES_CLK_3 (0x7 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 3
+#define PMC_MCKR_PLLDIV2 12 ///< PLL Divisor by 2
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_PCK[3] register.
+ */
+/*\{*/
+#define PMC_PCK_CSS_MASK 0x7 ///< Master Clock Source Selection mask
+#define PMC_PCK_CSS_SLOW 0x0 ///< Slow Clock is selected
+#define PMC_PCK_CSS_MAIN 0x1 ///< Main Clock is selected
+#define PMC_PCK_CSS_PLL 0x2 ///< PLL Clock is selected
+#define PMC_PCK_CSS_MCK 0x4 ///< Master Clock is selected
+#define PMC_PCK_PRES_SHIFT 4
+#define PMC_PCK_PRES_MASK (0x7 << PMC_PCK_PRES_SHIFT) ///< Programmable Clock Prescaler
+#define PMC_PCK_PRES_CLK (0x0 << PMC_PCK_PRES_SHIFT) ///< Selected clock
+#define PMC_PCK_PRES_CLK_2 (0x1 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 2
+#define PMC_PCK_PRES_CLK_4 (0x2 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 4
+#define PMC_PCK_PRES_CLK_8 (0x3 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 8
+#define PMC_PCK_PRES_CLK_16 (0x4 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 16
+#define PMC_PCK_PRES_CLK_32 (0x5 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 32
+#define PMC_PCK_PRES_CLK_64 (0x6 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 64
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_IER register.
+ */
+/*\{*/
+#define PMC_IER_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Enable
+#define PMC_IER_LOCK 1 ///< PLL Lock Interrupt Enable
+#define PMC_IER_MCKRDY 3 ///< Master Clock Ready Interrupt Enable
+#define PMC_IER_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Enable
+#define PMC_IER_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Enable
+#define PMC_IER_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Enable
+#define PMC_IER_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Enable
+#define PMC_IER_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Enable
+#define PMC_IER_CFDEV 18 ///< Clock Failure Detector Event Interrupt Enable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_IDR register.
+ */
+/*\{*/
+#define PMC_IDR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Disable
+#define PMC_IDR_LOCK 1 ///< PLL Lock Interrupt Disable
+#define PMC_IDR_MCKRDY 3 ///< Master Clock Ready Interrupt Disable
+#define PMC_IDR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Disable
+#define PMC_IDR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Disable
+#define PMC_IDR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Disable
+#define PMC_IDR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Disable
+#define PMC_IDR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Disable
+#define PMC_IDR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Disable
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_SR register.
+ */
+/*\{*/
+#define PMC_SR_MOSCXTS 0 ///< Main XTAL Oscillator Status
+#define PMC_SR_LOCK 1 ///< PLL Lock Status
+#define PMC_SR_MCKRDY 3 ///< Master Clock Status
+#define PMC_SR_OSCSELS 7 ///< Slow Clock Oscillator Selection
+#define PMC_SR_PCKRDY0 8 ///< Programmable Clock Ready Status
+#define PMC_SR_PCKRDY1 9 ///< Programmable Clock Ready Status
+#define PMC_SR_PCKRDY2 10 ///< Programmable Clock Ready Status
+#define PMC_SR_MOSCSELS 16 ///< Main Oscillator Selection Status
+#define PMC_SR_MOSCRCS 17 ///< Main On-Chip RC Oscillator Status
+#define PMC_SR_CFDEV 18 ///< Clock Failure Detector Event
+#define PMC_SR_CFDS 19 ///< Clock Failure Detector Status
+#define PMC_SR_FOS 20 ///< Clock Failure Detector Fault Output Status
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_IMR register.
+ */
+/*\{*/
+#define PMC_IMR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Mask
+#define PMC_IMR_LOCK 1 ///< PLL Lock Interrupt Mask
+#define PMC_IMR_MCKRDY 3 ///< Master Clock Ready Interrupt Mask
+#define PMC_IMR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Mask
+#define PMC_IMR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Mask
+#define PMC_IMR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Mask
+#define PMC_IMR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Mask
+#define PMC_IMR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Mask
+#define PMC_IMR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Mask
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_FSMR register.
+ */
+/*\{*/
+#define PMC_FSMR_FSTT0 0 ///< Fast Startup Input Enable 0
+#define PMC_FSMR_FSTT1 1 ///< Fast Startup Input Enable 1
+#define PMC_FSMR_FSTT2 2 ///< Fast Startup Input Enable 2
+#define PMC_FSMR_FSTT3 3 ///< Fast Startup Input Enable 3
+#define PMC_FSMR_FSTT4 4 ///< Fast Startup Input Enable 4
+#define PMC_FSMR_FSTT5 5 ///< Fast Startup Input Enable 5
+#define PMC_FSMR_FSTT6 6 ///< Fast Startup Input Enable 6
+#define PMC_FSMR_FSTT7 7 ///< Fast Startup Input Enable 7
+#define PMC_FSMR_FSTT8 8 ///< Fast Startup Input Enable 8
+#define PMC_FSMR_FSTT9 9 ///< Fast Startup Input Enable 9
+#define PMC_FSMR_FSTT10 10 ///< Fast Startup Input Enable 10
+#define PMC_FSMR_FSTT11 11 ///< Fast Startup Input Enable 11
+#define PMC_FSMR_FSTT12 12 ///< Fast Startup Input Enable 12
+#define PMC_FSMR_FSTT13 13 ///< Fast Startup Input Enable 13
+#define PMC_FSMR_FSTT14 14 ///< Fast Startup Input Enable 14
+#define PMC_FSMR_FSTT15 15 ///< Fast Startup Input Enable 15
+#define PMC_FSMR_RTTAL 16 ///< RTT Alarm Enable
+#define PMC_FSMR_RTCAL 17 ///< RTC Alarm Enable
+#define PMC_FSMR_LPM 20 ///< Low Power Mode
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_FSPR register.
+ */
+/*\{*/
+#define PMC_FSPR_FSTP0 0 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP1 1 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP2 2 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP3 3 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP4 4 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP5 5 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP6 6 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP7 7 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP8 8 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP9 9 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP10 10 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP11 11 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP12 12 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP13 13 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP14 14 ///< Fast Startup Input Polarityx
+#define PMC_FSPR_FSTP15 15 ///< Fast Startup Input Polarityx
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_FOCR register.
+ */
+/*\{*/
+#define PMC_FOCR_FOCLR 0 ///< Fault Output Clear
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_WPMR register.
+ */
+/*\{*/
+#define PMC_WPMR_WPEN 0 ///< Write Protect Enable
+#define PMC_WPMR_WPKEY_SHIFT 8
+#define PMC_WPMR_WPKEY_MASK (0xffffff << PMC_WPMR_WPKEY_SHIFT) ///< Write Protect key mask
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_WPSR register.
+ */
+/*\{*/
+#define PMC_WPSR_WPVS 0 ///< Write Protect Violation Status
+#define PMC_WPSR_WPVSRC_SHIFT 8
+#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) ///< Write Protect Violation Source mask
+/*\}*/
+
+/**
+ * Defines for bit fields in PMC_OCR register.
+ */
+/*\{*/
+#define PMC_OCR_CAL4_MASK 0x7f ///< RC Oscillator Calibration bits for 4 MHz mask
+#define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_MASK & (value))
+#define PMC_OCR_SEL4 7 ///< Selection of RC Oscillator Calibration bits for 4 MHz
+#define PMC_OCR_CAL8_SHIFT 8
+#define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) ///< RC Oscillator Calibration bits for 8 MHz mask
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))
+#define PMC_OCR_SEL8 15 ///< Selection of RC Oscillator Calibration bits for 8 MHz
+#define PMC_OCR_CAL12_SHIFT 16
+#define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) ///< RC Oscillator Calibration bits for 12 MHz mask
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))
+#define PMC_OCR_SEL12 23 ///< Selection of RC Oscillator Calibration bits for 12 MHz
+/*\}*/
+
+
+#endif /* SAM3_PMC_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief ATSAM3 system controller registers.
+ */
+
+#ifndef SAM3_SYSCTL_H
+#define SAM3_SYSCTL_H
+
+/** Supply controller base */
+#define SUPC_BASE 0x400E1410
+
+/**
+ * Supply controller offsets.
+ */
+/*\{*/
+#define SUPC_CR_OFF 0x0 ///< Supply Controller Control
+#define SUPC_SMMR_OFF 0x4 ///< Supply Controller Supply Monitor Mode
+#define SUPC_MR_OFF 0x8 ///< Supply Controller Mode
+#define SUPC_WUMR_OFF 0xC ///< Supply Controller Wake Up Mode
+#define SUPC_WUIR_OFF 0x10 ///< Supply Controller Wake Up Inputs
+#define SUPC_SR_OFF 0x14 ///< Supply Controller Status
+/*\}*/
+
+/**
+ * Supply controller registers.
+ */
+/*\{*/
+#define SUPC_CR (*((reg32_t *)(SUPC_BASE + SUPC_CR_OFF ))) ///< Supply Controller Control
+#define SUPC_SMMR (*((reg32_t *)(SUPC_BASE + SUPC_SMMR_OFF))) ///< Supply Controller Supply Monitor Mode
+#define SUPC_MR (*((reg32_t *)(SUPC_BASE + SUPC_MR_OFF ))) ///< Supply Controller Mode
+#define SUPC_WUMR (*((reg32_t *)(SUPC_BASE + SUPC_WUMR_OFF))) ///< Supply Controller Wake Up Mode
+#define SUPC_WUIR (*((reg32_t *)(SUPC_BASE + SUPC_WUIR_OFF))) ///< Supply Controller Wake Up Inputs
+#define SUPC_SR (*((reg32_t *)(SUPC_BASE + SUPC_SR_OFF ))) ///< Supply Controller Status
+/*\}*/
+
+/**
+ * Defines for bit fields in SUPC_CR register.
+ */
+/*\{*/
+#define SUPC_CR_VROFF 2 ///< Voltage Regulator Off
+#define SUPC_CR_XTALSEL 3 ///< Crystal Oscillator Select
+#define SUPC_CR_KEY_P 24
+#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_P) ///< SUPC_CR key
+#define SUPC_CR_KEY(value) (SUPC_CR_KEY_MASK & ((value) << SUPC_CR_KEY_P))
+/*\}*/
+
+/**
+ * Defines for bit fields in SUPC_SR register.
+ */
+/*\{*/
+#define SUPC_SR_WKUPS 1 ///< WKUP Wake Up Status
+#define SUPC_SR_SMWS 2 ///< Supply Monitor Detection Wake Up Status
+#define SUPC_SR_BODRSTS 3 ///< Brownout Detector Reset Status
+#define SUPC_SR_SMRSTS 4 ///< Supply Monitor Reset Status
+#define SUPC_SR_SMS 5 ///< Supply Monitor Status
+#define SUPC_SR_SMOS 6 ///< Supply Monitor Output Status
+#define SUPC_SR_OSCSEL 7 ///< 32-kHz Oscillator Selection Status
+#define SUPC_SR_WKUPIS0 16 ///< WKUP Input Status 0
+#define SUPC_SR_WKUPIS1 17 ///< WKUP Input Status 1
+#define SUPC_SR_WKUPIS2 18 ///< WKUP Input Status 2
+#define SUPC_SR_WKUPIS3 19 ///< WKUP Input Status 3
+#define SUPC_SR_WKUPIS4 20 ///< WKUP Input Status 4
+#define SUPC_SR_WKUPIS5 21 ///< WKUP Input Status 5
+#define SUPC_SR_WKUPIS6 22 ///< WKUP Input Status 6
+#define SUPC_SR_WKUPIS7 23 ///< WKUP Input Status 7
+#define SUPC_SR_WKUPIS8 24 ///< WKUP Input Status 8
+#define SUPC_SR_WKUPIS9 25 ///< WKUP Input Status 9
+#define SUPC_SR_WKUPIS10 26 ///< WKUP Input Status 10
+#define SUPC_SR_WKUPIS11 27 ///< WKUP Input Status 11
+#define SUPC_SR_WKUPIS12 28 ///< WKUP Input Status 12
+#define SUPC_SR_WKUPIS13 29 ///< WKUP Input Status 13
+#define SUPC_SR_WKUPIS14 30 ///< WKUP Input Status 14
+#define SUPC_SR_WKUPIS15 31 ///< WKUP Input Status 15
+/*\}*/
+
+#endif /* SAM3_SYSCTL_H */
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief AT91SAM3 UART hardware.
+ */
+
+#ifndef SAM3_UART_H
+#define SAM3_UART_H
+
+/**
+ * UART registers base addresses.
+ */
+/*\{*/
+#define UART0_BASE 0x400E0600
+#ifndef CPU_CM3_AT91SAM3U
+ #define UART1_BASE 0x400E0800
+#endif
+/*\}*/
+
+/**
+ * UART register offsets.
+ */
+/*\{*/
+#define UART_CR_OFF 0x000 //< Control Register
+#define UART_MR_OFF 0x004 //< Mode Register
+#define UART_IER_OFF 0x008 //< Interrupt Enable Register
+#define UART_IDR_OFF 0x00C //< Interrupt Disable Register
+#define UART_IMR_OFF 0x010 //< Interrupt Mask Register
+#define UART_SR_OFF 0x014 //< Status Register
+#define UART_RHR_OFF 0x018 //< Receive Holding Register
+#define UART_THR_OFF 0x01C //< Transmit Holding Register
+#define UART_BRGR_OFF 0x020 //< Baud Rate Generator Register
+
+#define UART_RPR_OFF 0x100 //< Receive Pointer Register
+#define UART_RCR_OFF 0x104 //< Receive Counter Register
+#define UART_TPR_OFF 0x108 //< Transmit Pointer Register
+#define UART_TCR_OFF 0x10C //< Transmit Counter Register
+#define UART_RNPR_OFF 0x110 //< Receive Next Pointer Register
+#define UART_RNCR_OFF 0x114 //< Receive Next Counter Register
+#define UART_TNPR_OFF 0x118 //< Transmit Next Pointer Register
+#define UART_TNCR_OFF 0x11C //< Transmit Next Counter Register
+#define UART_PTCR_OFF 0x120 //< Transfer Control Register
+#define UART_PTSR_OFF 0x124 //< Transfer Status Register
+/*\}*/
+
+/**
+ * UART register addresses.
+ */
+/*\{*/
+#if defined(UART0_BASE)
+ #define UART0_ACCESS(offset) (*((reg32_t *)(UART0_BASE + (offset))))
+
+ #define UART_CR UART0_ACCESS(UART_CR_OFF) //< Control Register
+ #define UART_MR UART0_ACCESS(UART_MR_OFF) //< Mode Register
+ #define UART_IER UART0_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
+ #define UART_IDR UART0_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
+ #define UART_IMR UART0_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
+ #define UART_SR UART0_ACCESS(UART_SR_OFF) //< Status Register
+ #define UART_RHR UART0_ACCESS(UART_RHR_OFF) //< Receive Holding Register
+ #define UART_THR UART0_ACCESS(UART_THR_OFF) //< Transmit Holding Register
+ #define UART_BRGR UART0_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
+
+ #define UART_RPR UART0_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
+ #define UART_RCR UART0_ACCESS(UART_RCR_OFF) //< Receive Counter Register
+ #define UART_TPR UART0_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
+ #define UART_TCR UART0_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
+ #define UART_RNPR UART0_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
+ #define UART_RNCR UART0_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
+ #define UART_TNPR UART0_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
+ #define UART_TNCR UART0_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
+ #define UART_PTCR UART0_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
+ #define UART_PTSR UART0_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
+#endif /* UART0_BASE */
+
+#if defined(UART1_BASE)
+ #define UART1_ACCESS(offset) (*((reg32_t *)(UART1_BASE + (offset))))
+
+ #define UART_CR UART1_ACCESS(UART_CR_OFF) //< Control Register
+ #define UART_MR UART1_ACCESS(UART_MR_OFF) //< Mode Register
+ #define UART_IER UART1_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
+ #define UART_IDR UART1_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
+ #define UART_IMR UART1_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
+ #define UART_SR UART1_ACCESS(UART_SR_OFF) //< Status Register
+ #define UART_RHR UART1_ACCESS(UART_RHR_OFF) //< Receive Holding Register
+ #define UART_THR UART1_ACCESS(UART_THR_OFF) //< Transmit Holding Register
+ #define UART_BRGR UART1_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
+
+ #define UART_RPR UART1_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
+ #define UART_RCR UART1_ACCESS(UART_RCR_OFF) //< Receive Counter Register
+ #define UART_TPR UART1_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
+ #define UART_TCR UART1_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
+ #define UART_RNPR UART1_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
+ #define UART_RNCR UART1_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
+ #define UART_TNPR UART1_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
+ #define UART_TNCR UART1_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
+ #define UART_PTCR UART1_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
+ #define UART_PTSR UART1_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
+#endif /* UART0_BASE */
+/*\}*/
+
+/**
+ * Bit fields in the UART_CR register.
+ */
+/*\{*/
+#define UART_CR_RSTRX 2 //< Reset Receiver
+#define UART_CR_RSTTX 3 //< Reset Transmitter
+#define UART_CR_RXEN 4 //< Receiver Enable
+#define UART_CR_RXDIS 5 //< Receiver Disable
+#define UART_CR_TXEN 6 //< Transmitter Enable
+#define UART_CR_TXDIS 7 //< Transmitter Disable
+#define UART_CR_RSTSTA 8 //< Reset Status Bits
+/*\}*/
+
+/**
+ * Bit fields in the UART_MR register.
+ */
+/*\{*/
+#define UART_MR_PAR_SHIFT 9 //< Parity Type shift
+#define UART_MR_PAR_MASK (0x7 << UART_MR_PAR_SHIFT) //< Parity Type mask
+#define UART_MR_PAR_EVEN (0x0 << UART_MR_PAR_SHIFT) //< Even parity
+#define UART_MR_PAR_ODD (0x1 << UART_MR_PAR_SHIFT) //< Odd parity
+#define UART_MR_PAR_SPACE (0x2 << UART_MR_PAR_SHIFT) //< Space: parity forced to 0
+#define UART_MR_PAR_MARK (0x3 << UART_MR_PAR_SHIFT) //< Mark: parity forced to 1
+#define UART_MR_PAR_NO (0x4 << UART_MR_PAR_SHIFT) //< No parity
+#define UART_MR_CHMODE_SHIFT 14 //< Channel Mode shift
+#define UART_MR_CHMODE_MASK (0x3 << UART_MR_CHMODE_SHIFT) //< Channel Mode mask
+#define UART_MR_CHMODE_NORMAL (0x0 << UART_MR_CHMODE_SHIFT) //< Normal Mode
+#define UART_MR_CHMODE_AUTOMATIC (0x1 << UART_MR_CHMODE_SHIFT) //< Automatic Echo
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SHIFT) //< Local Loopback
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SHIFT) //< Remote Loopback
+/*\}*/
+
+/**
+ * Bit fields in the UART_IER register.
+ */
+/*\{*/
+#define UART_IER_RXRDY 0 //< Enable RXRDY Interrupt
+#define UART_IER_TXRDY 1 //< Enable TXRDY Interrupt
+#define UART_IER_ENDRX 3 //< Enable End of Receive Transfer Interrupt
+#define UART_IER_ENDTX 4 //< Enable End of Transmit Interrupt
+#define UART_IER_OVRE 5 //< Enable Overrun Error Interrupt
+#define UART_IER_FRAME 6 //< Enable Framing Error Interrupt
+#define UART_IER_PARE 7 //< Enable Parity Error Interrupt
+#define UART_IER_TXEMPTY 9 //< Enable TXEMPTY Interrupt
+#define UART_IER_TXBUFE 11 //< Enable Buffer Empty Interrupt
+#define UART_IER_RXBUFF 12 //< Enable Buffer Full Interrupt
+/*\}*/
+
+/**
+ * Bit fields in the UART_IDR register.
+ */
+/*\{*/
+#define UART_IDR_RXRDY 0 //< Disable RXRDY Interrupt
+#define UART_IDR_TXRDY 1 //< Disable TXRDY Interrupt
+#define UART_IDR_ENDRX 3 //< Disable End of Receive Transfer Interrupt
+#define UART_IDR_ENDTX 4 //< Disable End of Transmit Interrupt
+#define UART_IDR_OVRE 5 //< Disable Overrun Error Interrupt
+#define UART_IDR_FRAME 6 //< Disable Framing Error Interrupt
+#define UART_IDR_PARE 7 //< Disable Parity Error Interrupt
+#define UART_IDR_TXEMPTY 9 //< Disable TXEMPTY Interrupt
+#define UART_IDR_TXBUFE 11 //< Disable Buffer Empty Interrupt
+#define UART_IDR_RXBUFF 12 //< Disable Buffer Full Interrupt
+/*\}*/
+
+/**
+ * Bit fields in the UART_IMR register.
+ */
+/*\{*/
+#define UART_IMR_RXRDY 0 //< Mask RXRDY Interrupt
+#define UART_IMR_TXRDY 1 //< Disable TXRDY Interrupt
+#define UART_IMR_ENDRX 3 //< Mask End of Receive Transfer Interrupt
+#define UART_IMR_ENDTX 4 //< Mask End of Transmit Interrupt
+#define UART_IMR_OVRE 5 //< Mask Overrun Error Interrupt
+#define UART_IMR_FRAME 6 //< Mask Framing Error Interrupt
+#define UART_IMR_PARE 7 //< Mask Parity Error Interrupt
+#define UART_IMR_TXEMPTY 9 //< Mask TXEMPTY Interrupt
+#define UART_IMR_TXBUFE 11 //< Mask TXBUFE Interrupt
+#define UART_IMR_RXBUFF 12 //< Mask RXBUFF Interrupt
+/*\}*/
+
+/**
+ * Bit fields in the UART_SR register.
+ */
+/*\{*/
+#define UART_SR_RXRDY 0 //< Receiver Ready
+#define UART_SR_TXRDY 1 //< Transmitter Ready
+#define UART_SR_ENDRX 3 //< End of Receiver Transfer
+#define UART_SR_ENDTX 4 //< End of Transmitter Transfer
+#define UART_SR_OVRE 5 //< Overrun Error
+#define UART_SR_FRAME 6 //< Framing Error
+#define UART_SR_PARE 7 //< Parity Error
+#define UART_SR_TXEMPTY 9 //< Transmitter Empty
+#define UART_SR_TXBUFE 11 //< Transmission Buffer Empty
+#define UART_SR_RXBUFF 12 //< Receive Buffer Full
+/*\}*/
+
+/**
+ * Bit fields in the UART_RHR register.
+ */
+/*\{*/
+#define UART_RHR_RXCHR_MASK 0xFF //< Received Character mask
+#define UART_RHR_RXCHR_SHIFT 0 //< Received Character shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_THR register.
+ */
+/*\{*/
+#define UART_THR_TXCHR_MASK 0xFF //< Character to be Transmitted mask
+#define UART_THR_TXCHR_SHIFT 0 //< Character to be Transmitted shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_BRGR register.
+ */
+/*\{*/
+#define UART_BRGR_CD_MASK 0xFFFF //< Clock Divisor mask
+#define UART_BRGR_CD_SHIFT 0 //< Clock Divisor shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_RPR register.
+ */
+/*\{*/
+#define UART_RPR_RXPTR_MASK 0xFFFFFFFF //< Receive Pointer Register mask
+#define UART_RPR_RXPTR_SHIFT 0 //< Receive Pointer Register shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_RCR register.
+ */
+/*\{*/
+#define UART_RCR_RXCTR_MASK 0xFFFF //< Receive Counter Register mask
+#define UART_RCR_RXCTR_SHIFT 0 //< Receive Counter Register shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_TPR register.
+ */
+/*\{*/
+#define UART_TPR_TXPTR_MASK 0xFFFFFFFF //< Transmit Counter Register mask
+#define UART_TPR_TXPTR_SHIFT 0 //< Transmit Counter Register shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_TCR register.
+ */
+/*\{*/
+#define UART_TCR_TXCTR_MASK 0xFFFF //< Transmit Counter Register mask
+#define UART_TCR_TXCTR_SHIFT 0 //< Transmit Counter Register shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_RNPR register.
+ */
+/*\{*/
+#define UART_RNPR_RXNPTR_MASK 0xFFFFFFFF //< Receive Next Pointer mask
+#define UART_RNPR_RXNPTR_SHIFT 0 //< Receive Next Pointer shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_RNCR register.
+ */
+/*\{*/
+#define UART_RNCR_RXNCTR_MASK 0xFFFF //< Receive Next Counter mask
+#define UART_RNCR_RXNCTR_SHIFT 0 //< Receive Next Counter shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_TNPR register.
+ */
+/*\{*/
+#define UART_TNPR_TXNPTR_MASK 0xFFFFFFFF //< Transmit Next Pointer mask
+#define UART_TNPR_TXNPTR_SHIFT 0 //< Transmit Next Pointer shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_TNCR register.
+ */
+/*\{*/
+#define UART_TNCR_TXNCTR_MASK 0xFFFF //< Transmit Counter Next mask
+#define UART_TNCR_TXNCTR_SHIFT 0 //< Transmit Counter Next shift
+/*\}*/
+
+/**
+ * Bit fields in the UART_PTCR register.
+ */
+/*\{*/
+#define UART_PTCR_RXTEN 0 //< Receiver Transfer Enable
+#define UART_PTCR_RXTDIS 1 //< Receiver Transfer Disable
+#define UART_PTCR_TXTEN 8 //< Transmitter Transfer Enable
+#define UART_PTCR_TXTDIS 9 //< Transmitter Transfer Disable
+/*\}*/
+
+/**
+ * Bit fields in the UART_PTSR register.
+ */
+/*\{*/
+#define UART_PTSR_RXTEN 0 //< Receiver Transfer Enable
+#define UART_PTSR_TXTEN 8 //< Transmitter Transfer Enable
+/*\}*/
+
+#endif /* SAM3_UART_H */
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