Remove unneeded config macros; Fix ser configuration.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@2568 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 725e5dd1b7dce98d48a41173c1503d78608eb505..2adb55eaa382e182f1d06dc738539344e657c9c4 100644 (file)
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -46,17 +46,6 @@
  * Edit these define for your project.
  */
 
-/// Serial port settings. $WIZ$ type = "int"
-#define CONFIG_SER_PORT      0
-/// Serial port baudrate. $WIZ$ type = "int"
-#define CONFIG_SER_BAUDRATE  115200UL
-
-/// Spi port settings. $WIZ$ type = "int"
-#define CONFIG_SPI_PORT      0
-/// Spi port baudrate. $WIZ$ type = "int"
-#define CONFIG_SPI_BAUDRATE  5000000UL
-
-
 /// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_TXBUFSIZE  32
 
@@ -70,10 +59,18 @@
 #define CONFIG_UART1_RXBUFSIZE  32
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
+/**
+ * [bytes] Size of the outbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
+/**
+ * [bytes] Size of the inbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_RXBUFSIZE    32
 
 /// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
@@ -89,27 +86,35 @@
 #define CONFIG_SPI1_RXBUFSIZE  32
 
 /**
- * SPI data order (AVR only).
+ * SPI data order.
  *
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_order_bit"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_DATA_ORDER  SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). $WIZ$ type = "int"
+/**
+ * SPI clock division factor.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_CLOCK_DIV   16
+
 /**
- * SPI clock polarity: normal low or normal high (AVR only).
+ * SPI clock polarity: normal low or normal high.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_pol"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
 /**
  * SPI clock phase you can choose sample on first edge or
- * sample on second clock edge (AVR only)
+ * sample on second clock edge.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_phase"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_CLOCK_PHASE     SPI_SAMPLE_ON_FIRST_EDGE
 

diff --git a/bertos/drv/dataflash_hwtest.c b/bertos/drv/dataflash_hwtest.c
index 3edf8111ac94b2ce546726b1c851a0c0dcb7f66e..fa5f480eea2cae9dc4de6beb3f5ffa726ca4b18b 100644 (file)
--- a/bertos/drv/dataflash_hwtest.c
+++ b/bertos/drv/dataflash_hwtest.c
@@ -130,10 +130,10 @@ int dataflash_testSetup(void)
          * Init SPI module and dataflash driver.
          */
         // Open SPI comunication channel
-        spimaster_init(&spi_fd, CONFIG_SPI_PORT);
+        spimaster_init(&spi_fd, 0);
         LOG_INFO("SPI0 init..ok\n");
 
-        ser_setbaudrate(&spi_fd, CONFIG_SPI_BAUDRATE);
+        ser_setbaudrate(&spi_fd, 5000000UL);
         LOG_INFO("SPI0 set baudrate..ok\n");
 
         //Init dataflash memory

diff --git a/examples/at91sam7s/cfg/cfg_ser.h b/examples/at91sam7s/cfg/cfg_ser.h
index c88fefe7fab476717400a571e8e995f08c385462..b9820e85b71004e07ee17a11c6771aac8c5e4ee7 100644 (file)
--- a/examples/at91sam7s/cfg/cfg_ser.h
+++ b/examples/at91sam7s/cfg/cfg_ser.h
@@ -45,14 +45,6 @@
  * spi port.
  * Edit these define for your project.
  */
-/// Serial settings
-#define CONFIG_SER_PORT      0
-#define CONFIG_SER_BAUDRATE  115200
-
-/// Spi settings
-#define CONFIG_SPI_PORT      0
-#define CONFIG_SPI_BAUDRATE  5000000UL
-
 
 /// [bytes] Size of the outbound FIFO buffer for port 0.
 #define CONFIG_UART0_TXBUFSIZE  32