/*#*
*#* $Log$
+ *#* Revision 1.9 2006/02/10 12:38:00 bernie
+ *#* Add support for ARM on IAR.
+ *#*
*#* Revision 1.8 2006/01/16 03:27:49 bernie
*#* Rename sig_t to sigbit_t to avoid clash with POSIX.
*#*
#if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__)
+
#pragma language=extended
- #define INTERRUPT(x) interrupt [x]
- #define REGISTER shortad
- #define INLINE /* unsupported */
- /*
- * Imported from <longjmp.h>. Unfortunately, we can't just include
- * this header because it typedefs jmp_buf to be an array of chars.
- * This would allow the compiler to place the buffer on an odd address.
- * The CPU _should_ be able to perform word accesses to
- * unaligned data, but there are *BUGS* in the 80196KC with
- * some combinations of opcodes and addressing modes. One of
- * these, "ST SP,[?GR]+" is used in the longjmp() implementation
- * provided by the IAR compiler ANSI C library. When ?GR contains
- * an odd address, surprisingly the CPU will copy the high order
- * byte of the source operand (SP) in the low order byte of the
- * destination operand (the memory location pointed to by ?GR).
- *
- * We also need to replace the library setjmp()/longjmp() with
- * our own versions because the IAR implementation "forgets" to
- * save the contents of local registers (?LR).
- */
- struct _JMP_BUF
- {
- void *sp; /* Stack pointer */
- void *return_addr; /* Return address */
- int lr[6]; /* 6 local registers */
- };
+ // IAR has size_t as built-in type, but does not define this symbol.
+ #define _SIZE_T_DEFINED
+
+ #ifdef CPU_ARM
+
+ #define COMPILER_VARIADIC_MACROS 1
+
+ #define INTERRUPT(x) __irq __arm void x (void)
+ #define REGISTER register
+ #define INLINE static inline
+
+ /* Include some standard C89/C99 stuff */
+ #include <stddef.h>
+ #include <stdbool.h>
- typedef struct _JMP_BUF jmp_buf[1];
+ #else /* CPU_I196 */
- int setjmp(jmp_buf env);
- void longjmp(jmp_buf env, int val);
+ #define INTERRUPT(x) interrupt [x]
+ #define REGISTER shortad
+ #define INLINE /* unsupported */
- /* Fake bool support */
- #define true (1==1)
- #define false (1!=1)
- typedef unsigned char bool;
+ /*
+ * Imported from <longjmp.h>. Unfortunately, we can't just include
+ * this header because it typedefs jmp_buf to be an array of chars.
+ * This would allow the compiler to place the buffer on an odd address.
+ * The CPU _should_ be able to perform word accesses to
+ * unaligned data, but there are *BUGS* in the 80196KC with
+ * some combinations of opcodes and addressing modes. One of
+ * these, "ST SP,[?GR]+" is used in the longjmp() implementation
+ * provided by the IAR compiler ANSI C library. When ?GR contains
+ * an odd address, surprisingly the CPU will copy the high order
+ * byte of the source operand (SP) in the low order byte of the
+ * destination operand (the memory location pointed to by ?GR).
+ *
+ * We also need to replace the library setjmp()/longjmp() with
+ * our own versions because the IAR implementation "forgets" to
+ * save the contents of local registers (?LR).
+ */
+ struct _JMP_BUF
+ {
+ void *sp; /* Stack pointer */
+ void *return_addr; /* Return address */
+ int lr[6]; /* 6 local registers */
+ };
+
+ typedef struct _JMP_BUF jmp_buf[1];
+
+ int setjmp(jmp_buf env);
+ void longjmp(jmp_buf env, int val);
+
+ /* Fake bool support */
+ #define true (1==1)
+ #define false (1!=1)
+ typedef unsigned char bool;
+
+ #endif /* !CPU_I196 */
#elif defined(_MSC_VER) /* Win32 emulation support */
/*!
* \def COMPILER_TYPEOF
- * Support for macros with variable arguments.
+ * Support for dynamic type identification.
*/
#ifndef COMPILER_TYPEOF
#define COMPILER_TYPEOF 0
/*!
* \def COMPILER_STATEMENT_EXPRESSIONS
- * Support for macros with variable arguments.
+ * Support for statement expressions.
*/
#ifndef COMPILER_STATEMENT_EXPRESSIONS
#define COMPILER_STATEMENT_EXPRESSIONS 0
/*#*
*#* $Log$
+ *#* Revision 1.8 2006/02/10 12:37:45 bernie
+ *#* Add support for ARM on IAR.
+ *#*
*#* Revision 1.7 2005/11/27 03:04:38 bernie
*#* Add POSIX emulation for IRQ_* macros; Add Qt support.
*#*
#define CPU_REG_BITS 32
#endif
+#elif CPU_ARM
+
+ #ifdef __IAR_SYSTEMS_ICC__
+
+ #include <inarm.h>
+
+ #define NOP __no_operation()
+ #define IRQ_DISABLE __disable_interrupt()
+ #define IRQ_ENABLE __enable_interrupt()
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ (x) = __get_CPSR(); \
+ __disable_interrupt(); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ __set_CPSR(x); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ((bool)(__get_CPSR() & 0xb0))
+
+ #else /* __IAR_SYSTEMS_ICC__ */
+
+ #warning "IRQ_ macros need testing!"
+
+ #define NOP asm volatile ("mov r0,r0" ::)
+
+ #define IRQ_DISABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "orr r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ :: \
+ ); \
+ } while (0)
+
+ #define IRQ_ENABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "bic r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ :: \
+ ); \
+ } while (0)
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "mov %0, r0\n\t" \
+ "orr r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ : "=r" (x) \
+ : /* no inputs */ \
+ : "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ asm volatile ( \
+ "mov r0, %0\n\t" \
+ "msr cpsr, r0" \
+ : /* no outputs */ \
+ : "r" (x) \
+ : "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ({ \
+ uint32_t sreg; \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "mov %0, r0" \
+ : "=r" (sreg)
+ : /* no inputs */
+ : "r0" \
+ ); \
+ (bool)(sreg & 0xb0); \
+ })
+
+ #endif /* __IAR_SYSTEMS_ICC_ */
+
+ typedef uint32_t cpuflags_t;
+ typedef uint32_t cpustack_t;
+
+ /* Register counts include SREG too */
+ #define CPU_REG_BITS 32
+ #define CPU_REGS_CNT 16
+ #define CPU_SAVED_REGS_CNT FIXME
+ #define CPU_STACK_GROWS_UPWARD 0 //FIXME
+ #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
+ #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+ #define CPU_HARVARD 0
+
#elif CPU_PPC
#define NOP asm volatile ("nop" ::)
/*#*
*#* $Log$
+ *#* Revision 1.3 2006/02/10 12:37:37 bernie
+ *#* Add support for ARM on IAR.
+ *#*
*#* Revision 1.2 2005/06/14 06:15:10 bernie
*#* Add X86_64 support.
*#*
#ifndef CPU_DETECT_H
#define CPU_DETECT_H
-#if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__)
- #define CPU_I196 1
+#if defined(__arm__) /* GCC */ \
+ || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */
+ #define CPU_ARM 1
+ #define CPU_ID arm
+#else
+ #define CPU_ARM 0
+#endif
+
+#if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \
+ && !defined(__ARM4TM__) /* IAR: if not ARM assume I196 */
+ #define CPU_I196 1
#define CPU_ID i196
#else
#define CPU_I196 0
/* Self-check for the detection: only one CPU must be detected */
-#if CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR == 0
+#if CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR == 0
#error Unknown CPU
#elif !defined(CPU_ID)
#error CPU_ID not defined
-#elif CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR != 1
+#elif CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR != 1
#error Internal CPU configuration error
#endif
projects / bertos.git / commitdiff