MT29F NAND flash driver: add block erase function.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4842 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/mt29f_sam3.c b/bertos/cpu/cortex-m3/drv/mt29f_sam3.c
index 89095f94aeb06040bd60ac90838a0222ac37dfc9..bd28a40547e2cfde2e9081037c66f8c89cadc607 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/mt29f_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/mt29f_sam3.c
@@ -57,12 +57,144 @@
 #include <string.h> /* memcpy() */
 
 
+// NAND flash status codes
+#define MT29F_STATUS_READY             BV(6)
+#define MT29F_STATUS_ERROR             BV(0)
+
+// NAND flash commands
+#define MT29F_CMD_READ_1               0x00
+#define MT29F_CMD_READ_2               0x30
+#define MT29F_CMD_COPYBACK_READ_1      0x00
+#define MT29F_CMD_COPYBACK_READ_2      0x35
+#define MT29F_CMD_COPYBACK_PROGRAM_1   0x85
+#define MT29F_CMD_COPYBACK_PROGRAM_2   0x10
+#define MT29F_CMD_RANDOM_OUT           0x05
+#define MT29F_CMD_RANDOM_OUT_2         0xE0
+#define MT29F_CMD_RANDOM_IN            0x85
+#define MT29F_CMD_READID               0x90
+#define MT29F_CMD_WRITE_1              0x80
+#define MT29F_CMD_WRITE_2              0x10
+#define MT29F_CMD_ERASE_1              0x60
+#define MT29F_CMD_ERASE_2              0xD0
+#define MT29F_CMD_STATUS               0x70
+#define MT29F_CMD_RESET                0xFF
+
+
 struct Mt29fHardware
 {
        int boh;
 };
 
 
+/*
+ * Translate flash memory offset in the five address cycles format
+ * needed by NAND.
+ *
+ * Cycles in x8 mode as the MT29F2G08AAD
+ * CA = column addr, PA = page addr, BA = block addr
+ *
+ * Cycle    I/O7  I/O6  I/O5  I/O4  I/O3  I/O2  I/O1  I/O0
+ * -------------------------------------------------------
+ * First    CA7   CA6   CA5   CA4   CA3   CA2   CA1   CA0
+ * Second   LOW   LOW   LOW   LOW   CA11  CA10  CA9   CA8
+ * Third    BA7   BA6   PA5   PA4   PA3   PA2   PA1   PA0
+ * Fourth   BA15  BA14  BA13  BA12  BA11  BA10  BA9   BA8
+ * Fifth    LOW   LOW   LOW   LOW   LOW   LOW   LOW   BA16
+ */
+static void mt29f_getAddrCycles(size_t offset, uint32_t *cycle0, uint32_t *cycle1234)
+{
+       /*
+        * offset nibbles  77776666 55554444 33332222 11110000
+        * cycle1234       -------7 66665555 ----4444 33332222
+        * cycle0          11110000
+        */
+       *cycle0 = offset & 0xFF;
+       *cycle1234 = ((offset >> 8) & 0x00000fff) | ((offset >> 4) & 0x01ff0000);
+}
+
+
+INLINE bool mt29f_isBusy(void)
+{
+       return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000;
+}
+
+INLINE bool mt29f_isCmdDone(void)
+{
+    return SMC_SR & SMC_SR_CMDDONE;
+}
+
+INLINE uint8_t mt29f_isReadyBusy(void)
+{
+    return SMC_SR & SMC_SR_RB_EDGE0;
+}
+
+
+/*
+ * Send command to NAND and wait for completion.
+ */
+static void mt29f_sendCommand(uint32_t cmd, uint32_t cycle0, uint32_t cycle1234)
+{
+       reg32_t *cmd_addr;
+
+       while (mt29f_isBusy());
+
+       SMC_ADDR = cycle0;
+
+       cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
+       *cmd_addr = cycle1234;
+
+       while (!mt29f_isCmdDone());
+}
+
+
+static bool mt29f_isOperationComplete(void)
+{
+       uint8_t status;
+
+       mt29f_sendCommand(
+               NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
+               MT29F_CMD_STATUS << 2, 0, 0);
+
+       status = (uint8_t)HWREG(MT29F_DATA_ADDR);
+       return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
+}
+
+
+#if 0 //reset
+       mt29f_sendCommand(
+                       NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
+                       MT29F_CMD_RESET << 2,
+                       0,                                     /* Dummy address cylce 1,2,3,4.*/
+                       0                                      /* Dummy address cylce 0.*/
+#endif
+
+/**
+ * Erase block at given offset.
+ */
+int mt29f_blockErase(Mt29f *fls, size_t blk_offset)
+{
+       uint32_t cycle0;
+       uint32_t cycle1234;
+
+       mt29f_getAddrCycles(blk_offset, &cycle0, &cycle1234);
+
+       mt29f_sendCommand(
+               NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
+               (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
+               cycle1234, 0);
+
+       while (!mt29f_isReadyBusy());
+
+       if (!mt29f_isOperationComplete())
+       {
+               LOG_ERR("mt29f: error erasing block\n");
+               return -1;
+       }
+
+       return 0;
+}
+
+
 static size_t mt29f_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size)
 {
 }
@@ -115,7 +247,6 @@ static const KBlockVTable mt29f_unbuffered_vt =
 
 
 static struct Mt29fHardware mt29f_hw;
-static uint8_t kblock_buf[MT29F_PAGE_SIZE];
 
 
 static void common_init(Mt29f *fls)
@@ -128,7 +259,10 @@ static void common_init(Mt29f *fls)
        fls->blk.blk_size = MT29F_PAGE_SIZE;
        fls->blk.blk_cnt =  MT29F_SIZE / MT29F_PAGE_SIZE;
 
-       // TODO: put following stuff in hw_ file dependent (and configurable cs?)
+       /*
+        * TODO: put following stuff in hw_ file dependent (and configurable cs?)
+        * Parameters for MT29F8G08AAD
+        */
        pmc_periphEnable(PIOA_ID);
        pmc_periphEnable(PIOC_ID);
        pmc_periphEnable(PIOD_ID);
@@ -170,17 +304,15 @@ static void common_init(Mt29f *fls)
 
     SMC_MODE0 = SMC_MODE_READ_MODE
                | SMC_MODE_WRITE_MODE;
-
-
 }
 
 
-void mt29f_hw_init(Mt29f *fls, int flags)
+void mt29f_hw_init(Mt29f *fls)
 {
        common_init(fls);
        fls->blk.priv.vt = &mt29f_buffered_vt;
        fls->blk.priv.flags |= KB_BUFFERED | KB_PARTIAL_WRITE;
-       fls->blk.priv.buf = kblock_buf;
+       fls->blk.priv.buf = (void *)NFC_CMD_BASE_ADDR;
 
        // Load the first block in the cache
        void *start = 0x0;
@@ -188,7 +320,7 @@ void mt29f_hw_init(Mt29f *fls, int flags)
 }
 
 
-void mt29f_hw_initUnbuffered(Mt29f *fls, int flags)
+void mt29f_hw_initUnbuffered(Mt29f *fls)
 {
        common_init(fls);
        fls->blk.priv.vt = &mt29f_unbuffered_vt;

diff --git a/bertos/cpu/cortex-m3/drv/mt29f_sam3.h b/bertos/cpu/cortex-m3/drv/mt29f_sam3.h
index a6108b06a489c66e21b36b5e3374ab619679745e..d15f64f6d7bb83adc395774cb631559af89b5d46 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/mt29f_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/mt29f_sam3.h
@@ -38,9 +38,20 @@
 #ifndef MT29F_SAM3_H
 #define MT29F_SAM3_H
 
+#include <drv/mt29f.h>
+
+
 // MT29F2G08AAD, FIXME: configurable
-#define MT29F_PAGE_SIZE  2048
-#define MT29F_SIZE       0x10000000  // 256 MB
+#define MT29F_PAGE_SIZE   0x800       // 2048 B
+#define MT29F_BLOCK_SIZE  0x20000     // 128 kB
+#define MT29F_SIZE        0x10000000  // 256 MB
+#define MT29F_CSID        NFC_CMD_CSID_0  // Chip select
+
+// Addresses for sending command, addresses and data bytes to flash
+#define MT29F_CMD_ADDR    0x60400000
+#define MT29F_ADDR_ADDR   0x60200000
+#define MT29F_DATA_ADDR   0x60000000
+
 
 /*
  * PIO definitions.
@@ -61,5 +72,9 @@
 #define MT29F_PINS_PORTD    (MT29F_PIN_CLE | MT29F_PIN_ALE)
 #define MT29F_PERIPH_PORTD  PIO_PERIPH_A
 
+
+int mt29f_blockErase(Mt29f *fls, size_t blk_offset);
+
+
 #endif /* MT29F_SAM3_H */
 

diff --git a/bertos/drv/mt29f.h b/bertos/drv/mt29f.h
index 0c3ee6b7b12e4b4eea476f698089e435fb7ad897..b5c466656c327289af8e6801c85325eb227779ad 100644 (file)
--- a/bertos/drv/mt29f.h
+++ b/bertos/drv/mt29f.h
@@ -99,7 +99,7 @@ INLINE Mt29f *FLASH_CAST(KBlock *fls)
        return (Mt29f *)fls;
 }
 
-void mt29f_hw_init(Mt29f *fls, int flags);
-void mt29f_hw_initUnbuffered(Mt29f *fls, int flags);
+void mt29f_hw_init(Mt29f *fls);
+void mt29f_hw_initUnbuffered(Mt29f *fls);
 
 #endif /* DRV_MT29F_H */