From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Tue, 6 Apr 2010 09:28:17 +0000 (+0000)
Subject: lm3s1968: delay few cycles after enabling the UART peripheral clock.
X-Git-Tag: 2.5.0~516
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=1126e7f2a95867585386149228c7a29427e6405c;p=bertos.git

lm3s1968: delay few cycles after enabling the UART peripheral clock.

Introduce a small spinning delay to give the oscillator time to
stabilize.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3392 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index e9061d36..7bcfc9ba 100644
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -37,6 +37,7 @@
 
 #include <cfg/macros.h> /* for BV() */
 #include "kdebug_lm3s.h"
+#include "clock_lm3s.h" /* __delay() */
 #include "cfg/cfg_debug.h"
 #include "io/lm3s.h"
 
@@ -123,6 +124,7 @@ INLINE void kdbg_hw_init(void)
 	/* Enable the peripheral clock */
 	SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
 	SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
+	__delay(512);
 
 	/* Set GPIO A0 and A1 as UART pins */
 	HWREG(GPIO_PORTA_BASE + GPIO_O_DIR) |= BV(0) | BV(1);