From: aleph <aleph@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Sat, 26 Mar 2011 17:34:48 +0000 (+0000)
Subject: sam3 eth: fix phy initialization.
X-Git-Tag: 2.7.0~154
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=1627174411f3fd5aba957b2908758e6df0ebe74f;p=bertos.git

sam3 eth: fix phy initialization.


git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4812 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.c b/bertos/cpu/cortex-m3/drv/eth_sam3.c
index 5e18dfe4..686da8ba 100644
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.c
@@ -181,25 +181,34 @@ static int emac_reset(void)
 	uint16_t phy_cr;
 	unsigned i;
 
+#if CPU_ARM_AT91
 	// Enable devices
-	//PMC_PCER = BV(PIOA_ID);
-	//PMC_PCER = BV(PIOB_ID);
-	//PMC_PCER = BV(EMAC_ID);
-	// TOOD: Implement in sam7x
-	pmc_periphEnable(PIOA_ID);
-	pmc_periphEnable(PIOB_ID);
-	pmc_periphEnable(EMAC_ID);
+	PMC_PCER = BV(PIOA_ID);
+	PMC_PCER = BV(PIOB_ID);
+	PMC_PCER = BV(EMAC_ID);
 
-	// Disable TESTMODE
+	// Disable TESTMODE and RMII
 	PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-#if CPU_ARM_AT91
-	// Disable RMII
 	PIOB_PUDR = BV(PHY_COL_RMII_BIT);
 
 	// Disable PHY power down.
 	PIOB_PER  = BV(PHY_PWRDN_BIT);
 	PIOB_OER  = BV(PHY_PWRDN_BIT);
 	PIOB_CODR = BV(PHY_PWRDN_BIT);
+#else
+	pmc_periphEnable(PIOA_ID);
+	pmc_periphEnable(PIOB_ID);
+	pmc_periphEnable(PIOC_ID);
+	pmc_periphEnable(PIOD_ID);
+	pmc_periphEnable(EMAC_ID);
+
+	// Disable TESTMODE and RMII
+	PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
+
+	// Disable PHY power down.
+	PIOD_PER  = BV(PHY_PWRDN_BIT);
+	PIOD_OER  = BV(PHY_PWRDN_BIT);
+	PIOD_CODR = BV(PHY_PWRDN_BIT);
 #endif
 
 	// Toggle external hardware reset pin.
@@ -214,11 +223,16 @@ static int emac_reset(void)
 	PIOB_ASR = PHY_MII_PINS;
 	PIOB_BSR = 0;
 	PIOB_PDR = PHY_MII_PINS;
+
 	// Enable receive and transmit clocks.
 	EMAC_USRIO = BV(EMAC_CLKEN);
 #else
-	PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS, PIO_PERIPH_A);
-	PIOB_PDR = PHY_MII_PINS;
+	PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
+	PIOB_PDR = PHY_MII_PINS_PORTB;
+
+	PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
+	PIOC_PDR = PHY_MII_PINS_PORTC;
+
 	// Enable receive, transmit clocks and RMII mode.
 	EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
 #endif
@@ -233,7 +247,7 @@ static int emac_reset(void)
 	EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
 
 	// Wait for PHY ready
-	timer_delay(255);
+	timer_delay(500);
 
 #if 0 // debug test
 	for (;;)
@@ -258,27 +272,18 @@ static int emac_reset(void)
 #endif
 
 	// Clear MII isolate.
-	phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
+	//phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
 	phy_cr = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
 
 	phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
 	phy_hw_write(NIC_PHY_ADDR, NIC_PHY_BMCR, phy_cr);
 
-	phy_cr = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
+	//phy_cr = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
 
 	LOG_INFO("%s: PHY ID %#04x %#04x\n",
 		__func__,
 		phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ID1), phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ID2));
 
-	// Wait for auto negotiation completed.
-	phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR);
-	for (;;)
-	{
-		if (phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
-			break;
-		cpu_relax();
-	}
-
 	// Disable management port.
 	EMAC_NCR &= ~BV(EMAC_MPE);
 
diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.h b/bertos/cpu/cortex-m3/drv/eth_sam3.h
index 04d4aab6..bd5e6f32 100644
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.h
@@ -128,27 +128,32 @@
 #define PHY_TXEN_BIT            1
 #define PHY_TXD0_BIT            2
 #define PHY_TXD1_BIT            3
-#define PHY_RXDV_TESTMODE_BIT   4
 #define PHY_RXD0_AD0_BIT        5
 #define PHY_RXD1_AD1_BIT        6
 #define PHY_RXER_RXD4_RPTR_BIT  7
 #define PHY_MDC_BIT             8
 #define PHY_MDIO_BIT            9
+// Port C
+#define PHY_RXDV_TESTMODE_BIT   10
 // Port A
 #define PHY_MDINTR_BIT          5
+// Port D -- FIXME: Only on which revision?
+#define PHY_PWRDN_BIT           18
 
-#define PHY_MII_PINS \
+#define PHY_MII_PINS_PORTB \
 	BV(PHY_REFCLK_XT2_BIT) \
 	| BV(PHY_TXEN_BIT) \
 	| BV(PHY_TXD0_BIT) \
 	| BV(PHY_TXD1_BIT) \
-	| BV(PHY_RXDV_TESTMODE_BIT) \
 	| BV(PHY_RXD0_AD0_BIT) \
 	| BV(PHY_RXD1_AD1_BIT) \
 	| BV(PHY_RXER_RXD4_RPTR_BIT) \
 	| BV(PHY_MDC_BIT) \
 	| BV(PHY_MDIO_BIT)
 
+#define PHY_MII_PINS_PORTC \
+	BV(PHY_RXDV_TESTMODE_BIT)
+
 #endif /* CPU_ARM_AT91 */
 // \}