From: aleph Date: Tue, 5 Oct 2010 16:45:35 +0000 (+0000) Subject: sam3n: add flash definitions and linker script X-Git-Tag: 2.6.0~5^2~108 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=1ae40c676a839d7f523d62da03687af22f877261;p=bertos.git sam3n: add flash definitions and linker script git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4412 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h index 46425493..b40381e5 100644 --- a/bertos/cpu/cortex-m3/io/sam3.h +++ b/bertos/cpu/cortex-m3/io/sam3.h @@ -48,5 +48,6 @@ #include "sam3_gpio.h" #include "sam3_nvic.h" #include "sam3_uart.h" +#include "sam3_flash.h" #endif /* SAM3_H */ diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h new file mode 100644 index 00000000..03cca342 --- /dev/null +++ b/bertos/cpu/cortex-m3/io/sam3_flash.h @@ -0,0 +1,94 @@ +/** + * \file + * + * + * \brief ATSAM3 enhanced embedded flash controller definitions. + */ + +#ifndef SAM3_FLASH_H +#define SAM3_FLASH_H + +/** + * EEFC registers. + */ +/*\{*/ +#define EEFC_FMR_R (*((reg32_t *)0x400E0A00)) ///< Flash Mode Register +#define EEFC_FCR_R (*((reg32_t *)0x400E0A04)) ///< Flash Command Register +#define EEFC_FSR_R (*((reg32_t *)0x400E0A08)) ///< Flash Status Register +#define EEFC_FRR_R (*((reg32_t *)0x400E0A0C)) ///< Flash Result Register +/*\}*/ + +/** + * EFC register addresses. + */ +/*\{*/ +#define EEFC_FMR 0x400E0A00 ///< Flash Mode Register +#define EEFC_FCR 0x400E0A04 ///< Flash Command Register +#define EEFC_FSR 0x400E0A08 ///< Flash Status Register +#define EEFC_FRR 0x400E0A0C ///< Flash Result Register +/*\}*/ + + +/** + * Defines for bit fields in EEFC_FMR register. + */ +/*\{*/ +#define EEFC_FMR_FRDY BV(0) ///< Ready Interrupt Enable +#define EEFC_FMR_FWS_S 8 +#define EEFC_FMR_FWS_M (0xf << EEFC_FMR_FWS_S) ///< Flash Wait State +#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_M & ((value) << EEFC_FMR_FWS_S)) +#define EEFC_FMR_FAM BV(24) ///< Flash Access Mode +/*\}*/ + +/** + * Defines for bit fields in EEFC_FCR register. + */ +/*\{*/ +#define EEFC_FCR_FCMD_M 0xff ///< Flash Command +#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_M & (value)) +#define EEFC_FCR_FARG_S 8 +#define EEFC_FCR_FARG_M (0xffff << EEFC_FCR_FARG_S) ///< Flash Command Argument +#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_M & ((value) << EEFC_FCR_FARG_S)) +#define EEFC_FCR_FKEY_S 24 +#define EEFC_FCR_FKEY_M (0xff << EEFC_FCR_FKEY_S) ///< Flash Writing Protection Key +#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_M & ((value) << EEFC_FCR_FKEY_S)) +/*\}*/ + +/** + * Defines for bit fields in EEFC_FSR register. + */ +/*\{*/ +#define EEFC_FSR_FRDY BV(0) ///< Flash Ready Status +#define EEFC_FSR_FCMDE BV(1) ///< Flash Command Error Status +#define EEFC_FSR_FLOCKE BV(2) ///< Flash Lock Error Status +/*\}*/ + +#endif /* SAM3_FLASH_H */ diff --git a/bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld b/bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld new file mode 100644 index 00000000..323f044a --- /dev/null +++ b/bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld @@ -0,0 +1,49 @@ +/** + * \file + * + * + * \author Stefano Fedrigo + * + * \brief Linker script for AT91SAM3N4 Cortex M3 processor. + * + */ + +/* + * Memory configuration for AT91SAM3N4. + */ +MEMORY +{ + rom(rx) : org = 0x0, len = 256k + ram(rwx) : org = 0x20000000, len = 24k +} + +INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_rom.ld" +