From: batt Date: Thu, 11 Oct 2007 15:08:57 +0000 (+0000) Subject: Move avr timer to avr cpu dir. X-Git-Tag: 1.0.0~379 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=29ae4cbcd0ce21d9327b7cff52ad3a11ec8102cd;p=bertos.git Move avr timer to avr cpu dir. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@862 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/cpu/avr/drv/timer_avr.c b/cpu/avr/drv/timer_avr.c new file mode 100644 index 00000000..736026d4 --- /dev/null +++ b/cpu/avr/drv/timer_avr.c @@ -0,0 +1,268 @@ +/** + * \file + * + * + * \version $Id$ + * + * \author Bernardo Innocenti + * \author Francesco Sacchi + * + * \brief Low-level timer module for AVR (implementation). + */ + +/*#* + *#* $Log$ + *#* Revision 1.6 2007/06/07 14:35:12 batt + *#* Merge from project_ks. + *#* + *#* Revision 1.5 2007/03/21 11:03:56 batt + *#* Add missing support for ATMega1281. + *#* + *#* Revision 1.4 2006/07/19 12:56:26 bernie + *#* Convert to new Doxygen style. + *#* + *#* Revision 1.3 2006/06/12 21:37:02 marco + *#* implemented some commands (ver and sleep) + *#* + *#* Revision 1.2 2006/05/18 00:37:58 bernie + *#* Don't include unneeded header hw.h. + *#* + *#* Revision 1.1 2005/07/19 07:28:36 bernie + *#* Refactor to decouple timer ticks from milliseconds. + *#* + *#* Revision 1.1 2005/05/24 09:17:58 batt + *#* Move drivers to top-level. + *#* + *#*/ +#include +#include // BV() + +#include + +#include +#include + +#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 + #define REG_TIFR0 TIFR0 + #define REG_TIFR2 TIFR2 + + #define REG_TIMSK0 TIMSK0 + #define REG_TIMSK2 TIMSK2 + + #define REG_TCCR2A TCCR2A + #define REG_TCCR2B TCCR2B + + #define REG_OCR2A OCR2A + + #define BIT_OCF0A OCF0A + #define BIT_OCF2A OCF2A + + #define BIT_OCIE0A OCIE0A + #define BIT_OCIE2A OCIE2A +#else + #define REG_TIFR0 TIFR + #define REG_TIFR2 TIFR + + #define REG_TIMSK0 TIMSK + #define REG_TIMSK2 TIMSK + + #define REG_TCCR2A TCCR2 + #define REG_TCCR2B TCCR2 + + #define REG_OCR2A OCR2 + + #define BIT_OCF0A OCF0 + #define BIT_OCF2A OCF2 + + #define BIT_OCIE0A OCIE0 + #define BIT_OCIE2A OCIE2 +#endif + + +/** HW dependent timer initialization */ +#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) + + static void timer_hw_init(void) + { + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer flags */ + REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); + + /* Setup Timer/Counter interrupt */ + ASSR = 0x00; /* Internal system clock */ + TCCR0 = BV(WGM01) /* Clear on Compare match */ + #if TIMER_PRESCALER == 64 + | BV(CS02) + #else + #error Unsupported value of TIMER_PRESCALER + #endif + ; + TCNT0 = 0x00; /* Initialization of Timer/Counter */ + OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ + + /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ + REG_TIMSK0 &= ~BV(TOIE0); + REG_TIMSK0 |= BV(OCIE0); + + IRQ_RESTORE(flags); + } + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT0; + } + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) + + static void timer_hw_init(void) + { + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer overflow flag */ + TIFR |= BV(TOV1); + + /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ + #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) + TCCR1A |= BV(WGM11); + TCCR1A &= ~BV(WGM10); + TCCR1B |= BV(WGM12) | BV(CS10); + TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); + /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ + #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) + TCCR1A |= BV(WGM10); + TCCR1A &= ~BV(WGM11); + TCCR1B |= BV(WGM12) | BV(CS10); + TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); + #else + #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS + #endif + + TCNT1 = 0x00; /* initialization of Timer/Counter */ + + /* Enable timer interrupt: Timer/Counter1 Overflow */ + TIMSK |= BV(TOIE1); + + IRQ_RESTORE(flags); + } + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT1; + } + +#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) + static void timer_hw_init(void) + { + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer flags */ + REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); + + /* Setup Timer/Counter interrupt */ + REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to + REG_TCCR2B = 0; // ensure correct initialization. + + REG_TCCR2A = BV(WGM21); + #if TIMER_PRESCALER == 64 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 + // ATMega1281 & ATMega168 have undocumented differences in timer2 prescaler! + REG_TCCR2B |= BV(CS22); + #else + REG_TCCR2B |= BV(CS21) | BV(CS20); + #endif + #else + #error Unsupported value of TIMER_PRESCALER + #endif + + /* Clear on Compare match & prescaler = 64, internal sys clock. + When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ + TCNT2 = 0x00; /* initialization of Timer/Counter */ + REG_OCR2A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ + + /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ + REG_TIMSK2 &= ~BV(TOIE2); + REG_TIMSK2 |= BV(BIT_OCIE2A); + + IRQ_RESTORE(flags); + } + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT2; + } +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) + + static void timer_hw_init(void) + { + cpuflags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer overflow flag */ + TIFR |= BV(TOV3); + + /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ + #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) + TCCR3A |= BV(WGM31); + TCCR3A &= ~BV(WGM30); + TCCR3B |= BV(WGM32) | BV(CS30); + TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); + /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ + #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) + TCCR3A |= BV(WGM30); + TCCR3A &= ~BV(WGM31); + TCCR3B |= BV(WGM32) | BV(CS30); + TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); + #else + #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS + #endif + + TCNT3 = 0x00; /* initialization of Timer/Counter */ + + /* Enable timer interrupt: Timer/Counter3 Overflow */ + /* ATTENTION! TOIE3 is only on ETIMSK, not TIMSK */ + ETIMSK |= BV(TOIE3); + + IRQ_RESTORE(flags); + } + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT3; + } + +#else + #error Unimplemented value for CONFIG_TIMER +#endif /* CONFIG_TIMER */ + diff --git a/cpu/avr/drv/timer_avr.h b/cpu/avr/drv/timer_avr.h new file mode 100644 index 00000000..5d0eba36 --- /dev/null +++ b/cpu/avr/drv/timer_avr.h @@ -0,0 +1,185 @@ +/** + * \file + * + * + * \version $Id$ + * + * \author Bernardo Innocenti + * \author Francesco Sacchi + * + * \brief Low-level timer module for AVR (interface). + */ + +/*#* + *#* $Log$ + *#* Revision 1.32 2007/10/08 12:14:32 batt + *#* Fix some review issues. + *#* + *#* Revision 1.31 2007/10/07 12:30:55 batt + *#* Add default timer for AVR. + *#* + *#* Revision 1.30 2007/06/07 14:35:12 batt + *#* Merge from project_ks. + *#* + *#* Revision 1.29 2007/03/21 11:01:36 batt + *#* Add missing support for ATMega1281. + *#* + *#* Revision 1.28 2006/07/19 12:56:26 bernie + *#* Convert to new Doxygen style. + *#* + *#* Revision 1.27 2006/05/18 00:38:24 bernie + *#* Use hw_cpu.h instead of ubiquitous hw.h. + *#* + *#* Revision 1.26 2006/02/21 21:28:02 bernie + *#* New time handling based on TIMER_TICKS_PER_SEC to support slow timers with ticks longer than 1ms. + *#* + *#* Revision 1.25 2005/07/19 07:26:37 bernie + *#* Refactor to decouple timer ticks from milliseconds. + *#* + *#* Revision 1.24 2005/04/11 19:10:28 bernie + *#* Include top-level headers from cfg/ subdir. + *#* + *#* Revision 1.23 2005/03/01 23:24:51 bernie + *#* Tweaks for avr-libc 1.2.x. + *#* + *#* Revision 1.21 2004/12/13 12:07:06 bernie + *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE. + *#* + *#* Revision 1.20 2004/11/16 20:59:46 bernie + *#* Include explicitly. + *#* + *#* Revision 1.19 2004/10/19 08:56:41 bernie + *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong. + *#* + *#* Revision 1.18 2004/09/20 03:31:03 bernie + *#* Fix racy racy code. + *#*/ +#ifndef DRV_TIMER_AVR_H +#define DRV_TIMER_AVR_H + +#include /* CONFIG_TIMER */ +#include /* uint8_t */ +#include /* CLOCK_FREQ */ + +/** + * \name Values for CONFIG_TIMER. + * + * Select which hardware timer interrupt to use for system clock and softtimers. + * \note The timer 1 overflow mode set the timer as a 24 kHz PWM. + * + * \{ + */ +#define TIMER_ON_OUTPUT_COMPARE0 1 +#define TIMER_ON_OVERFLOW1 2 +#define TIMER_ON_OUTPUT_COMPARE2 3 +#define TIMER_ON_OVERFLOW3 4 + +#define TIMER_DEFAULT TIMER_ON_OUTPUT_COMPARE0 ///< Default system timer +/* \} */ + +/* + * Hardware dependent timer initialization. + */ +#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) + + #define TIMER_PRESCALER 64 + #define TIMER_HW_BITS 8 + #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE0) + #define TIMER_TICKS_PER_SEC 1000 + #define TIMER_HW_CNT OCR_DIVISOR + + /// Type of time expressed in ticks of the hardware high-precision timer + typedef uint8_t hptime_t; + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) + + #define TIMER_PRESCALER 1 + #define TIMER_HW_BITS 8 + /** This value is the maximum in overflow based timers. */ + #define TIMER_HW_CNT (1 << TIMER_HW_BITS) + #define DEFINE_TIMER_ISR SIGNAL(SIG_OVERFLOW1) + #define TIMER_TICKS_PER_SEC ((TIMER_HW_HPTICKS_PER_SEC + TIMER_HW_CNT / 2) / TIMER_HW_CNT) + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint16_t hptime_t; + +#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) + + #define TIMER_PRESCALER 64 + #define TIMER_HW_BITS 8 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 + #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE2A) + #else + #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE2) + #endif + #define TIMER_TICKS_PER_SEC 1000 + /** Value for OCR register in output-compare based timers. */ + #define TIMER_HW_CNT OCR_DIVISOR + + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint8_t hptime_t; + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) + + #define TIMER_PRESCALER 1 + #define TIMER_HW_BITS 8 + /** This value is the maximum in overflow based timers. */ + #define TIMER_HW_CNT (1 << TIMER_HW_BITS) + #define DEFINE_TIMER_ISR SIGNAL(SIG_OVERFLOW3) + #define TIMER_TICKS_PER_SEC ((TIMER_HW_HPTICKS_PER_SEC + TIMER_HW_CNT / 2) / TIMER_HW_CNT) + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint16_t hptime_t; +#else + + #error Unimplemented value for CONFIG_TIMER +#endif /* CONFIG_TIMER */ + + +/** Frequency of the hardware high precision timer. */ +#define TIMER_HW_HPTICKS_PER_SEC ((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER) + +/** + * System timer: additional division after the prescaler + * 12288000 / 64 / 192 (0..191) = 1 ms + */ +#define OCR_DIVISOR (((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER + TIMER_TICKS_PER_SEC / 2) / TIMER_TICKS_PER_SEC - 1) + +/** Not needed, IRQ timer flag cleared automatically */ +#define timer_hw_irq() do {} while (0) + +/** Not needed, timer IRQ handler called only for timer source */ +#define timer_hw_triggered() (true) + + +#endif /* DRV_TIMER_AVR_H */ diff --git a/drv/timer_avr.c b/drv/timer_avr.c deleted file mode 100644 index 736026d4..00000000 --- a/drv/timer_avr.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - * \file - * - * - * \version $Id$ - * - * \author Bernardo Innocenti - * \author Francesco Sacchi - * - * \brief Low-level timer module for AVR (implementation). - */ - -/*#* - *#* $Log$ - *#* Revision 1.6 2007/06/07 14:35:12 batt - *#* Merge from project_ks. - *#* - *#* Revision 1.5 2007/03/21 11:03:56 batt - *#* Add missing support for ATMega1281. - *#* - *#* Revision 1.4 2006/07/19 12:56:26 bernie - *#* Convert to new Doxygen style. - *#* - *#* Revision 1.3 2006/06/12 21:37:02 marco - *#* implemented some commands (ver and sleep) - *#* - *#* Revision 1.2 2006/05/18 00:37:58 bernie - *#* Don't include unneeded header hw.h. - *#* - *#* Revision 1.1 2005/07/19 07:28:36 bernie - *#* Refactor to decouple timer ticks from milliseconds. - *#* - *#* Revision 1.1 2005/05/24 09:17:58 batt - *#* Move drivers to top-level. - *#* - *#*/ -#include -#include // BV() - -#include - -#include -#include - -#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 - #define REG_TIFR0 TIFR0 - #define REG_TIFR2 TIFR2 - - #define REG_TIMSK0 TIMSK0 - #define REG_TIMSK2 TIMSK2 - - #define REG_TCCR2A TCCR2A - #define REG_TCCR2B TCCR2B - - #define REG_OCR2A OCR2A - - #define BIT_OCF0A OCF0A - #define BIT_OCF2A OCF2A - - #define BIT_OCIE0A OCIE0A - #define BIT_OCIE2A OCIE2A -#else - #define REG_TIFR0 TIFR - #define REG_TIFR2 TIFR - - #define REG_TIMSK0 TIMSK - #define REG_TIMSK2 TIMSK - - #define REG_TCCR2A TCCR2 - #define REG_TCCR2B TCCR2 - - #define REG_OCR2A OCR2 - - #define BIT_OCF0A OCF0 - #define BIT_OCF2A OCF2 - - #define BIT_OCIE0A OCIE0 - #define BIT_OCIE2A OCIE2 -#endif - - -/** HW dependent timer initialization */ -#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) - - static void timer_hw_init(void) - { - cpuflags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer flags */ - REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); - - /* Setup Timer/Counter interrupt */ - ASSR = 0x00; /* Internal system clock */ - TCCR0 = BV(WGM01) /* Clear on Compare match */ - #if TIMER_PRESCALER == 64 - | BV(CS02) - #else - #error Unsupported value of TIMER_PRESCALER - #endif - ; - TCNT0 = 0x00; /* Initialization of Timer/Counter */ - OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ - - /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ - REG_TIMSK0 &= ~BV(TOIE0); - REG_TIMSK0 |= BV(OCIE0); - - IRQ_RESTORE(flags); - } - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT0; - } - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) - - static void timer_hw_init(void) - { - cpuflags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer overflow flag */ - TIFR |= BV(TOV1); - - /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ - #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) - TCCR1A |= BV(WGM11); - TCCR1A &= ~BV(WGM10); - TCCR1B |= BV(WGM12) | BV(CS10); - TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); - /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ - #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) - TCCR1A |= BV(WGM10); - TCCR1A &= ~BV(WGM11); - TCCR1B |= BV(WGM12) | BV(CS10); - TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); - #else - #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS - #endif - - TCNT1 = 0x00; /* initialization of Timer/Counter */ - - /* Enable timer interrupt: Timer/Counter1 Overflow */ - TIMSK |= BV(TOIE1); - - IRQ_RESTORE(flags); - } - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT1; - } - -#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) - static void timer_hw_init(void) - { - cpuflags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer flags */ - REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); - - /* Setup Timer/Counter interrupt */ - REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to - REG_TCCR2B = 0; // ensure correct initialization. - - REG_TCCR2A = BV(WGM21); - #if TIMER_PRESCALER == 64 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 - // ATMega1281 & ATMega168 have undocumented differences in timer2 prescaler! - REG_TCCR2B |= BV(CS22); - #else - REG_TCCR2B |= BV(CS21) | BV(CS20); - #endif - #else - #error Unsupported value of TIMER_PRESCALER - #endif - - /* Clear on Compare match & prescaler = 64, internal sys clock. - When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ - TCNT2 = 0x00; /* initialization of Timer/Counter */ - REG_OCR2A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ - - /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ - REG_TIMSK2 &= ~BV(TOIE2); - REG_TIMSK2 |= BV(BIT_OCIE2A); - - IRQ_RESTORE(flags); - } - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT2; - } -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) - - static void timer_hw_init(void) - { - cpuflags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer overflow flag */ - TIFR |= BV(TOV3); - - /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ - #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) - TCCR3A |= BV(WGM31); - TCCR3A &= ~BV(WGM30); - TCCR3B |= BV(WGM32) | BV(CS30); - TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); - /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ - #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) - TCCR3A |= BV(WGM30); - TCCR3A &= ~BV(WGM31); - TCCR3B |= BV(WGM32) | BV(CS30); - TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); - #else - #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS - #endif - - TCNT3 = 0x00; /* initialization of Timer/Counter */ - - /* Enable timer interrupt: Timer/Counter3 Overflow */ - /* ATTENTION! TOIE3 is only on ETIMSK, not TIMSK */ - ETIMSK |= BV(TOIE3); - - IRQ_RESTORE(flags); - } - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT3; - } - -#else - #error Unimplemented value for CONFIG_TIMER -#endif /* CONFIG_TIMER */ - diff --git a/drv/timer_avr.h b/drv/timer_avr.h deleted file mode 100644 index 5d0eba36..00000000 --- a/drv/timer_avr.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * - * \version $Id$ - * - * \author Bernardo Innocenti - * \author Francesco Sacchi - * - * \brief Low-level timer module for AVR (interface). - */ - -/*#* - *#* $Log$ - *#* Revision 1.32 2007/10/08 12:14:32 batt - *#* Fix some review issues. - *#* - *#* Revision 1.31 2007/10/07 12:30:55 batt - *#* Add default timer for AVR. - *#* - *#* Revision 1.30 2007/06/07 14:35:12 batt - *#* Merge from project_ks. - *#* - *#* Revision 1.29 2007/03/21 11:01:36 batt - *#* Add missing support for ATMega1281. - *#* - *#* Revision 1.28 2006/07/19 12:56:26 bernie - *#* Convert to new Doxygen style. - *#* - *#* Revision 1.27 2006/05/18 00:38:24 bernie - *#* Use hw_cpu.h instead of ubiquitous hw.h. - *#* - *#* Revision 1.26 2006/02/21 21:28:02 bernie - *#* New time handling based on TIMER_TICKS_PER_SEC to support slow timers with ticks longer than 1ms. - *#* - *#* Revision 1.25 2005/07/19 07:26:37 bernie - *#* Refactor to decouple timer ticks from milliseconds. - *#* - *#* Revision 1.24 2005/04/11 19:10:28 bernie - *#* Include top-level headers from cfg/ subdir. - *#* - *#* Revision 1.23 2005/03/01 23:24:51 bernie - *#* Tweaks for avr-libc 1.2.x. - *#* - *#* Revision 1.21 2004/12/13 12:07:06 bernie - *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE. - *#* - *#* Revision 1.20 2004/11/16 20:59:46 bernie - *#* Include explicitly. - *#* - *#* Revision 1.19 2004/10/19 08:56:41 bernie - *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong. - *#* - *#* Revision 1.18 2004/09/20 03:31:03 bernie - *#* Fix racy racy code. - *#*/ -#ifndef DRV_TIMER_AVR_H -#define DRV_TIMER_AVR_H - -#include /* CONFIG_TIMER */ -#include /* uint8_t */ -#include /* CLOCK_FREQ */ - -/** - * \name Values for CONFIG_TIMER. - * - * Select which hardware timer interrupt to use for system clock and softtimers. - * \note The timer 1 overflow mode set the timer as a 24 kHz PWM. - * - * \{ - */ -#define TIMER_ON_OUTPUT_COMPARE0 1 -#define TIMER_ON_OVERFLOW1 2 -#define TIMER_ON_OUTPUT_COMPARE2 3 -#define TIMER_ON_OVERFLOW3 4 - -#define TIMER_DEFAULT TIMER_ON_OUTPUT_COMPARE0 ///< Default system timer -/* \} */ - -/* - * Hardware dependent timer initialization. - */ -#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) - - #define TIMER_PRESCALER 64 - #define TIMER_HW_BITS 8 - #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE0) - #define TIMER_TICKS_PER_SEC 1000 - #define TIMER_HW_CNT OCR_DIVISOR - - /// Type of time expressed in ticks of the hardware high-precision timer - typedef uint8_t hptime_t; - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) - - #define TIMER_PRESCALER 1 - #define TIMER_HW_BITS 8 - /** This value is the maximum in overflow based timers. */ - #define TIMER_HW_CNT (1 << TIMER_HW_BITS) - #define DEFINE_TIMER_ISR SIGNAL(SIG_OVERFLOW1) - #define TIMER_TICKS_PER_SEC ((TIMER_HW_HPTICKS_PER_SEC + TIMER_HW_CNT / 2) / TIMER_HW_CNT) - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint16_t hptime_t; - -#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) - - #define TIMER_PRESCALER 64 - #define TIMER_HW_BITS 8 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 - #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE2A) - #else - #define DEFINE_TIMER_ISR SIGNAL(SIG_OUTPUT_COMPARE2) - #endif - #define TIMER_TICKS_PER_SEC 1000 - /** Value for OCR register in output-compare based timers. */ - #define TIMER_HW_CNT OCR_DIVISOR - - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint8_t hptime_t; - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) - - #define TIMER_PRESCALER 1 - #define TIMER_HW_BITS 8 - /** This value is the maximum in overflow based timers. */ - #define TIMER_HW_CNT (1 << TIMER_HW_BITS) - #define DEFINE_TIMER_ISR SIGNAL(SIG_OVERFLOW3) - #define TIMER_TICKS_PER_SEC ((TIMER_HW_HPTICKS_PER_SEC + TIMER_HW_CNT / 2) / TIMER_HW_CNT) - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint16_t hptime_t; -#else - - #error Unimplemented value for CONFIG_TIMER -#endif /* CONFIG_TIMER */ - - -/** Frequency of the hardware high precision timer. */ -#define TIMER_HW_HPTICKS_PER_SEC ((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER) - -/** - * System timer: additional division after the prescaler - * 12288000 / 64 / 192 (0..191) = 1 ms - */ -#define OCR_DIVISOR (((CLOCK_FREQ + TIMER_PRESCALER / 2) / TIMER_PRESCALER + TIMER_TICKS_PER_SEC / 2) / TIMER_TICKS_PER_SEC - 1) - -/** Not needed, IRQ timer flag cleared automatically */ -#define timer_hw_irq() do {} while (0) - -/** Not needed, timer IRQ handler called only for timer source */ -#define timer_hw_triggered() (true) - - -#endif /* DRV_TIMER_AVR_H */