From: aleph <aleph@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Fri, 25 Feb 2011 10:32:40 +0000 (+0000)
Subject: sam3 serial: define and generalize peripheral assignement (A, B, C,...) to serial... 
X-Git-Tag: 2.7.0~239
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=3c19a25efb0e397dff784a40ae94c47858a58eff;p=bertos.git

sam3 serial: define and generalize peripheral assignement (A, B, C,...) to serial I/O ports


git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4727 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
index 3edf1305..d2b0cd81 100644
--- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c
@@ -41,15 +41,17 @@
 #include <io/sam3.h>
 
 
-#if CONFIG_KDEBUG_PORT == 0
+#if (CONFIG_KDEBUG_PORT == 0)
 	#define UART_BASE       UART0_BASE
 	#define UART_ID         UART0_ID
-	#define UART_PIO_BASE   PIOA_BASE
+	#define UART_PIO_BASE   UART0_PORT
+	#define UART_PERIPH     UART0_PERIPH
 	#define UART_PINS       (BV(URXD0) | BV(UTXD0))
 #elif (CONFIG_KDEBUG_PORT == 1) && UART_PORTS > 1
 	#define UART_BASE       UART1_BASE
 	#define UART_ID         UART1_ID
-	#define UART_PIO_BASE   PIOB_BASE
+	#define UART_PIO_BASE   UART1_PORT
+	#define UART_PERIPH     UART1_PERIPH
 	#define UART_PINS       (BV(URXD1) | BV(UTXD1))
 #else
 	#error "UART port not supported in this board"
@@ -77,7 +79,7 @@ INLINE void kdbg_hw_init(void)
 	 * SAM3X,A,N,S,U: all of them has all UARTs on peripheral A.
 	 */
 	HWREG(UART_PIO_BASE + PIO_PDR_OFF) = UART_PINS;
-	PIO_PERIPH_SEL(UART_PIO_BASE, UART_PINS, PIO_PERIPH_A);
+	PIO_PERIPH_SEL(UART_PIO_BASE, UART_PINS, UART_PERIPH);
 
 	/* Enable the peripheral clock */
 	PMC_PCER = BV(UART_ID);
diff --git a/bertos/cpu/cortex-m3/drv/ser_sam3.c b/bertos/cpu/cortex-m3/drv/ser_sam3.c
index d9c2bc65..8c2f764e 100644
--- a/bertos/cpu/cortex-m3/drv/ser_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/ser_sam3.c
@@ -91,7 +91,7 @@
 	#endif
 	#define SER_UART0_BUS_TXINIT do { \
 		PIOA_PDR = BV(RXD0) | BV(TXD0); \
-		PIO_PERIPH_SEL(PIOA_BASE, BV(RXD0) | BV(TXD0), PIO_PERIPH_A); \
+		PIO_PERIPH_SEL(PIOA_BASE, BV(RXD0) | BV(TXD0), USART0_PERIPH); \
 	} while (0)
 #endif
 
@@ -133,7 +133,7 @@
 		#endif
 		#define SER_UART1_BUS_TXINIT do { \
 			PIOA_PDR = BV(RXD1) | BV(TXD1); \
-			PIO_PERIPH_SEL(PIOA_BASE, BV(RXD1) | BV(TXD1), PIO_PERIPH_A); \
+			PIO_PERIPH_SEL(PIOA_BASE, BV(RXD1) | BV(TXD1), USART1_PERIPH); \
 		} while (0)
 	#endif
 
diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 429c3d5e..33ee560e 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -171,36 +171,70 @@
  */
 /*\{*/
 #if CPU_CM3_SAM3U
-	#define URXD0   11  // Port A
-	#define UTXD0   12  // Port A
-	#define RXD0    19  // Port A
-	#define TXD0    18  // Port A
-	#define RXD1    21  // Port A
-	#define TXD1    20  // Port A
-	#define RXD2    23  // Port A
-	#define TXD2    22  // Port A
-	#define RXD3    13  // Port C
-	#define TXD3    12  // Port C
+	#define UART0_PORT   PIOA_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+	#define USART2_PORT  PIOA_BASE
+	#define USART3_PORT  PIOC_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+	#define USART2_PERIPH  PIO_PERIPH_A
+	#define USART3_PERIPH  PIO_PERIPH_B
+
+	#define URXD0   11
+	#define UTXD0   12
+	#define RXD0    19
+	#define TXD0    18
+	#define RXD1    21
+	#define TXD1    20
+	#define RXD2    23
+	#define TXD2    22
+	#define RXD3    13
+	#define TXD3    12
 #elif CPU_CM3_SAM3X
-	#define URXD0    8  // Port A
-	#define UTXD0    9  // Port A
-	#define RXD0    10  // Port A
-	#define TXD0    11  // Port A
-	#define RXD1    12  // Port A
-	#define TXD1    13  // Port A
-	#define RXD2    21  // Port B
-	#define TXD2    20  // Port B
-	#define RXD3     5  // Port D
-	#define TXD3     4  // Port D
+	#define UART0_PORT   PIOA_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+	#define USART2_PORT  PIOB_BASE
+	#define USART3_PORT  PIOD_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+	#define USART2_PERIPH  PIO_PERIPH_A
+	#define USART3_PERIPH  PIO_PERIPH_B
+
+	#define URXD0    8
+	#define UTXD0    9
+	#define RXD0    10
+	#define TXD0    11
+	#define RXD1    12
+	#define TXD1    13
+	#define RXD2    21
+	#define TXD2    20
+	#define RXD3     5
+	#define TXD3     4
 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
-	#define URXD0    9  // Port A
-	#define UTXD0   10  // Port A
-	#define URXD1    2  // Port B
-	#define UTXD1    3  // Port B
-	#define RXD0     5  // Port A
-	#define TXD0     6  // Port A
-	#define RXD1    21  // Port A
-	#define TXD1    22  // Port A
+	#define UART0_PORT   PIOA_BASE
+	#define UART1_PORT   PIOB_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define UART1_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+
+	#define URXD0    9
+	#define UTXD0   10
+	#define URXD1    2
+	#define UTXD1    3
+	#define RXD0     5
+	#define TXD0     6
+	#define RXD1    21
+	#define TXD1    22
 #endif
 /*\}*/