From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Mon, 29 Mar 2010 14:40:43 +0000 (+0000)
Subject: lm3s1968: try to evaluate the correct SYSDIV value depending on the desired CPU frequ... 
X-Git-Tag: 2.5.0~605
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=49f2d09a180dc6e50dcc9f995fc2ba0ca3daea11;p=bertos.git

lm3s1968: try to evaluate the correct SYSDIV value depending on the desired CPU frequency.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3302 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/clock.c b/bertos/cpu/cortex-m3/drv/clock.c
index 3618185b..f3d31ec5 100644
--- a/bertos/cpu/cortex-m3/drv/clock.c
+++ b/bertos/cpu/cortex-m3/drv/clock.c
@@ -106,6 +106,7 @@ unsigned long clock_get_rate(void)
 void clock_set_rate(void)
 {
 	reg32_t rcc, rcc2;
+	unsigned long clk;
 	int i;
 
 	rcc = HWREG(SYSCTL_RCC);
@@ -158,14 +159,23 @@ void clock_set_rate(void)
 	 * frequency for the microcontroller.
 	 */
 	rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
-	for (i = 0; i < 15; i++)
+
+	/*
+	 * Try to evaluate the correct SYSDIV value depending on the desired
+	 * CPU frequency.
+	 */
+	clk = RCC_TO_CLK(rcc);
+	for (i = 0; i < 16; i++)
 	{
-		if (CPU_FREQ == RCC_TO_CLK(rcc))
+		clk = clk / (i + 1);
+		if (CPU_FREQ >= clk)
 			break;
-		rcc |= SYSCTL_RCC_USESYSDIV;
 	}
 	if (i)
+	{
+		rcc |= SYSCTL_RCC_USESYSDIV;
 		rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT;
+	}
 
 	/*
 	 * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the