From: asterix Date: Tue, 3 Aug 2010 10:49:23 +0000 (+0000) Subject: Add comment and reorder the includes. Move gpio structure to specific header file. X-Git-Tag: 2.6.0~264 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=4a5c3f8849defa78a7a65b3fa8a4c9c782952ffe;p=bertos.git Add comment and reorder the includes. Move gpio structure to specific header file. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4126 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/drv/gpio_stm32.c b/bertos/cpu/cortex-m3/drv/gpio_stm32.c index f15145a4..552d15b6 100644 --- a/bertos/cpu/cortex-m3/drv/gpio_stm32.c +++ b/bertos/cpu/cortex-m3/drv/gpio_stm32.c @@ -35,10 +35,13 @@ * \author Andrea Righi */ +#include "gpio_stm32.h" + #include #include + #include -#include "gpio_stm32.h" + /** * Configure a GPIO pin diff --git a/bertos/cpu/cortex-m3/drv/gpio_stm32.h b/bertos/cpu/cortex-m3/drv/gpio_stm32.h index 4d09db47..1314bfdb 100644 --- a/bertos/cpu/cortex-m3/drv/gpio_stm32.h +++ b/bertos/cpu/cortex-m3/drv/gpio_stm32.h @@ -38,22 +38,10 @@ #include -/* GPIO configuration registers structure */ -struct stm32_gpio -{ - reg32_t CRL; - reg32_t CRH; - reg32_t IDR; - reg32_t ODR; - reg32_t BSRR; - reg32_t BRR; - reg32_t LCKR; -}; - /** * GPIO mode + * \{ */ -/*\{*/ enum { GPIO_MODE_AIN = 0x0, @@ -69,8 +57,8 @@ enum /** * GPIO speed + *\{ */ -/*\{*/ enum { GPIO_SPEED_10MHZ = 1, @@ -79,9 +67,14 @@ enum }; /*\}*/ -/* Write a value to the specified pin(s) */ -INLINE void -stm32_gpioPinWrite(struct stm32_gpio *base, uint32_t pins, uint8_t val) +/** + * Write a value to the specified pin(s) + * + * \param base gpio register address + * \param pins mask of pins that we want set or clear + * \param val true to set selected pins of false to clear they. + */ +INLINE void stm32_gpioPinWrite(struct stm32_gpio *base, uint32_t pins, bool val) { if (val) base->BSRR |= pins; @@ -89,14 +82,25 @@ stm32_gpioPinWrite(struct stm32_gpio *base, uint32_t pins, uint8_t val) base->BRR |= pins; } -/* Read a value from the specified pin(s) */ +/** + * Read a value from the specified pin(s) + * + * \param base gpio register address + * \param pins mask of pins that we want read + */ INLINE uint8_t stm32_gpioPinRead(struct stm32_gpio *base, uint32_t pins) { return !!(base->IDR & pins); } -/* Initialize a GPIO peripheral configuration */ -int stm32_gpioPinConfig(struct stm32_gpio *base, - uint16_t pins, uint8_t mode, uint8_t speed); +/** + * Initialize a GPIO peripheral configuration + * + * \param base gpio register address + * \param pins mask of pins that we want to configure + * \param mode select the behaviour of selected pins + * \param speed clock frequency for selected gpio ports + */ +int stm32_gpioPinConfig(struct stm32_gpio *base, uint16_t pins, uint8_t mode, uint8_t speed); #endif /* GPIO_STM32_H */ diff --git a/bertos/cpu/cortex-m3/io/stm32_gpio.h b/bertos/cpu/cortex-m3/io/stm32_gpio.h new file mode 100644 index 00000000..71a6094c --- /dev/null +++ b/bertos/cpu/cortex-m3/io/stm32_gpio.h @@ -0,0 +1,55 @@ +/** + * \file + * + * + * \brief STM32F103xx GPIO definition. + */ + +#ifndef STM32_GPIO_H +#define STM32_GPIO_H + +#include + +/** + * GPIO configuration registers structure + */ +struct stm32_gpio +{ + reg32_t CRL; + reg32_t CRH; + reg32_t IDR; + reg32_t ODR; + reg32_t BSRR; + reg32_t BRR; + reg32_t LCKR; +}; + +#endif /* STM32_GPIO_H */