From: lottaviano Date: Sat, 9 Apr 2011 13:43:40 +0000 (+0000) Subject: Move AVR timer files to prepare XMega patches. X-Git-Tag: 2.7.0~118 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=4c9e017d1b5cad3501d8d93aef46ec513bb03fd0;p=bertos.git Move AVR timer files to prepare XMega patches. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4848 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/avr/drv/timer_avr.c b/bertos/cpu/avr/drv/timer_avr.c deleted file mode 100644 index ee63e76f..00000000 --- a/bertos/cpu/avr/drv/timer_avr.c +++ /dev/null @@ -1,259 +0,0 @@ -/** - * \file - * - * - * \author Bernie Innocenti - * \author Francesco Sacchi - * \author Luca Ottaviano - * - * \brief Low-level timer module for AVR (implementation). - * - * This module is automatically included so no need to include - * in test list. - * notest: avr - */ - -#include -#include // BV() - -#include -#include - -#include - -#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 - #define REG_TIFR0 TIFR0 - #define REG_TIFR1 TIFR1 - #define REG_TIFR2 TIFR2 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 - #define REG_TIFR3 TIFR3 - #endif - - #define REG_TIMSK0 TIMSK0 - #define REG_TIMSK1 TIMSK1 - #define REG_TIMSK2 TIMSK2 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 - #define REG_TIMSK3 TIMSK3 - #endif - - #define REG_TCCR0A TCCR0A - #define REG_TCCR0B TCCR0B - - #define REG_TCCR2A TCCR2A - #define REG_TCCR2B TCCR2B - - #define REG_OCR0A OCR0A - #define REG_OCR2A OCR2A - - #define BIT_OCF0A OCF0A - #define BIT_OCF2A OCF2A - - #define BIT_OCIE0A OCIE0A - #define BIT_OCIE2A OCIE2A -#else - #define REG_TIFR0 TIFR - #define REG_TIFR1 TIFR - #define REG_TIFR2 TIFR - #define REG_TIFR3 TIFR - - #define REG_TIMSK0 TIMSK - #define REG_TIMSK1 TIMSK - #define REG_TIMSK2 TIMSK - #define REG_TIMSK3 ETIMSK - - #define REG_TCCR0A TCCR0 - #define REG_TCCR0B TCCR0 - - #define REG_TCCR2A TCCR2 - #define REG_TCCR2B TCCR2 - - #define REG_OCR0A OCR0 - #define REG_OCR2A OCR2 - - #define BIT_OCF0A OCF0 - #define BIT_OCF2A OCF2 - - #define BIT_OCIE0A OCIE0 - #define BIT_OCIE2A OCIE2 -#endif - -#if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103 - /* These ATMega have different prescaler options. */ - #define TIMER0_PRESCALER_64 BV(CS02) - #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20)) -#else - #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00)) - #define TIMER2_PRESCALER_64 BV(CS22) -#endif - -/** HW dependent timer initialization */ -#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) - - void timer_hw_init(void) - { - cpu_flags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer flags */ - REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); - - /* Setup Timer/Counter interrupt */ - ASSR = 0x00; /* Internal system clock */ - - REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to - REG_TCCR0B = 0; - - REG_TCCR0A = BV(WGM01); /* Clear on Compare match */ - #if TIMER_PRESCALER == 64 - REG_TCCR0B |= TIMER0_PRESCALER_64; - #else - #error Unsupported value of TIMER_PRESCALER - #endif - - TCNT0 = 0x00; /* Initialization of Timer/Counter */ - REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ - - /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ - REG_TIMSK0 &= ~BV(TOIE0); - REG_TIMSK0 |= BV(BIT_OCIE0A); - - IRQ_RESTORE(flags); - } - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) - - void timer_hw_init(void) - { - cpu_flags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer overflow flag */ - REG_TIFR1 |= BV(TOV1); - - /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ - #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) - TCCR1A |= BV(WGM11); - TCCR1A &= ~BV(WGM10); - TCCR1B |= BV(WGM12) | BV(CS10); - TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); - /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ - #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) - TCCR1A |= BV(WGM10); - TCCR1A &= ~BV(WGM11); - TCCR1B |= BV(WGM12) | BV(CS10); - TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); - #else - #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS - #endif - - TCNT1 = 0x00; /* initialization of Timer/Counter */ - - /* Enable timer interrupt: Timer/Counter1 Overflow */ - REG_TIMSK1 |= BV(TOIE1); - - IRQ_RESTORE(flags); - } - -#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) - void timer_hw_init(void) - { - cpu_flags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer flags */ - REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); - - /* Setup Timer/Counter interrupt */ - REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to - REG_TCCR2B = 0; // ensure correct initialization. - - REG_TCCR2A = BV(WGM21); - #if TIMER_PRESCALER == 64 - REG_TCCR2B |= TIMER2_PRESCALER_64; - #else - #error Unsupported value of TIMER_PRESCALER - #endif - - /* Clear on Compare match & prescaler = 64, internal sys clock. - When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ - TCNT2 = 0x00; /* initialization of Timer/Counter */ - REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */ - - /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ - REG_TIMSK2 &= ~BV(TOIE2); - REG_TIMSK2 |= BV(BIT_OCIE2A); - - IRQ_RESTORE(flags); - } - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) - - #if CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32 - #error For select target there is not TIMER_ON_OVERFLOW3, please select an other one. - #endif - - void timer_hw_init(void) - { - cpu_flags_t flags; - IRQ_SAVE_DISABLE(flags); - - /* Reset Timer overflow flag */ - REG_TIFR3 |= BV(TOV3); - - /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ - #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) - TCCR3A |= BV(WGM31); - TCCR3A &= ~BV(WGM30); - TCCR3B |= BV(WGM32) | BV(CS30); - TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); - /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ - #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) - TCCR3A |= BV(WGM30); - TCCR3A &= ~BV(WGM31); - TCCR3B |= BV(WGM32) | BV(CS30); - TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); - #else - #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS - #endif - - /* initialization of Timer/Counter */ - TCNT3 = 0x00; - - /* Enable timer interrupt: Timer/Counter3 Overflow */ - REG_TIMSK3 |= BV(TOIE3); - - IRQ_RESTORE(flags); - } - -#else - #error Unimplemented value for CONFIG_TIMER -#endif /* CONFIG_TIMER */ - diff --git a/bertos/cpu/avr/drv/timer_avr.h b/bertos/cpu/avr/drv/timer_avr.h deleted file mode 100644 index 2146620c..00000000 --- a/bertos/cpu/avr/drv/timer_avr.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * \file - * - * - * \brief Low-level timer module for AVR (interface). - * - * \author Bernie Innocenti - * \author Francesco Sacchi - * \author Luca Ottaviano - * - */ - -#ifndef DRV_TIMER_AVR_H -#define DRV_TIMER_AVR_H - -#include /* CPU_FREQ */ - -#include "cfg/cfg_timer.h" /* CONFIG_TIMER */ -#include /* uint8_t */ -#include /* DIV_ROUND */ - -#include -#include - -/** - * \name Values for CONFIG_TIMER. - * - * Select which hardware timer interrupt to use for system clock and softtimers. - * \note The timer 1 overflow mode set the timer as a 24 kHz PWM. - * $WIZ$ timer_select = "TIMER_ON_OUTPUT_COMPARE0", "TIMER_ON_OVERFLOW1", "TIMER_ON_OUTPUT_COMPARE2", "TIMER_ON_OVERFLOW3", "TIMER_DEFAULT" - */ -#define TIMER_ON_OUTPUT_COMPARE0 1 -#define TIMER_ON_OVERFLOW1 2 -#define TIMER_ON_OUTPUT_COMPARE2 3 -#define TIMER_ON_OVERFLOW3 4 - -#define TIMER_DEFAULT TIMER_ON_OUTPUT_COMPARE0 ///< Default system timer - -/* - * Hardware dependent timer initialization. - */ -#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) - - #define TIMER_PRESCALER 64 - #define TIMER_HW_BITS 8 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMPA_vect) - #else - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMP_vect) - #endif - #define TIMER_TICKS_PER_SEC 1000 - #define TIMER_HW_CNT OCR_DIVISOR - - /// Type of time expressed in ticks of the hardware high-precision timer - typedef uint8_t hptime_t; - #define SIZEOF_HPTIME_T 1 - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT0; - } - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) - - #define TIMER_PRESCALER 1 - #define TIMER_HW_BITS 8 - /** This value is the maximum in overflow based timers. */ - #define TIMER_HW_CNT (1 << TIMER_HW_BITS) - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER1_OVF_vect) - #define TIMER_TICKS_PER_SEC DIV_ROUND(TIMER_HW_HPTICKS_PER_SEC, TIMER_HW_CNT) - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint16_t hptime_t; - #define SIZEOF_HPTIME_T 2 - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT1; - } - -#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) - - #define TIMER_PRESCALER 64 - #define TIMER_HW_BITS 8 - #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMPA_vect) - #else - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMP_vect) - #endif - #define TIMER_TICKS_PER_SEC 1000 - /** Value for OCR register in output-compare based timers. */ - #define TIMER_HW_CNT OCR_DIVISOR - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint8_t hptime_t; - #define SIZEOF_HPTIME_T 1 - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT2; - } - -#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) - - #define TIMER_PRESCALER 1 - #define TIMER_HW_BITS 8 - /** This value is the maximum in overflow based timers. */ - #define TIMER_HW_CNT (1 << TIMER_HW_BITS) - #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER3_OVF_vect) - #define TIMER_TICKS_PER_SEC DIV_ROUND(TIMER_HW_HPTICKS_PER_SEC, TIMER_HW_CNT) - - /// Type of time expressed in ticks of the hardware high precision timer - typedef uint16_t hptime_t; - #define SIZEOF_HPTIME_T 2 - - INLINE hptime_t timer_hw_hpread(void) - { - return TCNT3; - } - -#else - - #error Unimplemented value for CONFIG_TIMER -#endif /* CONFIG_TIMER */ - - -/** Frequency of the hardware high precision timer. */ -#define TIMER_HW_HPTICKS_PER_SEC DIV_ROUND(CPU_FREQ, TIMER_PRESCALER) - -/** - * System timer: additional division after the prescaler - * 12288000 / 64 / 192 (0..191) = 1 ms - */ -#define OCR_DIVISOR (DIV_ROUND(DIV_ROUND(CPU_FREQ, TIMER_PRESCALER), TIMER_TICKS_PER_SEC) - 1) - -/** Not needed, IRQ timer flag cleared automatically */ -#define timer_hw_irq() do {} while (0) - -/** Not needed, timer IRQ handler called only for timer source */ -#define timer_hw_triggered() (true) - -void timer_hw_init(void); - -#endif /* DRV_TIMER_AVR_H */ diff --git a/bertos/cpu/avr/drv/timer_mega.c b/bertos/cpu/avr/drv/timer_mega.c new file mode 100644 index 00000000..ee63e76f --- /dev/null +++ b/bertos/cpu/avr/drv/timer_mega.c @@ -0,0 +1,259 @@ +/** + * \file + * + * + * \author Bernie Innocenti + * \author Francesco Sacchi + * \author Luca Ottaviano + * + * \brief Low-level timer module for AVR (implementation). + * + * This module is automatically included so no need to include + * in test list. + * notest: avr + */ + +#include +#include // BV() + +#include +#include + +#include + +#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 + #define REG_TIFR0 TIFR0 + #define REG_TIFR1 TIFR1 + #define REG_TIFR2 TIFR2 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 + #define REG_TIFR3 TIFR3 + #endif + + #define REG_TIMSK0 TIMSK0 + #define REG_TIMSK1 TIMSK1 + #define REG_TIMSK2 TIMSK2 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 + #define REG_TIMSK3 TIMSK3 + #endif + + #define REG_TCCR0A TCCR0A + #define REG_TCCR0B TCCR0B + + #define REG_TCCR2A TCCR2A + #define REG_TCCR2B TCCR2B + + #define REG_OCR0A OCR0A + #define REG_OCR2A OCR2A + + #define BIT_OCF0A OCF0A + #define BIT_OCF2A OCF2A + + #define BIT_OCIE0A OCIE0A + #define BIT_OCIE2A OCIE2A +#else + #define REG_TIFR0 TIFR + #define REG_TIFR1 TIFR + #define REG_TIFR2 TIFR + #define REG_TIFR3 TIFR + + #define REG_TIMSK0 TIMSK + #define REG_TIMSK1 TIMSK + #define REG_TIMSK2 TIMSK + #define REG_TIMSK3 ETIMSK + + #define REG_TCCR0A TCCR0 + #define REG_TCCR0B TCCR0 + + #define REG_TCCR2A TCCR2 + #define REG_TCCR2B TCCR2 + + #define REG_OCR0A OCR0 + #define REG_OCR2A OCR2 + + #define BIT_OCF0A OCF0 + #define BIT_OCF2A OCF2 + + #define BIT_OCIE0A OCIE0 + #define BIT_OCIE2A OCIE2 +#endif + +#if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103 + /* These ATMega have different prescaler options. */ + #define TIMER0_PRESCALER_64 BV(CS02) + #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20)) +#else + #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00)) + #define TIMER2_PRESCALER_64 BV(CS22) +#endif + +/** HW dependent timer initialization */ +#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) + + void timer_hw_init(void) + { + cpu_flags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer flags */ + REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); + + /* Setup Timer/Counter interrupt */ + ASSR = 0x00; /* Internal system clock */ + + REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to + REG_TCCR0B = 0; + + REG_TCCR0A = BV(WGM01); /* Clear on Compare match */ + #if TIMER_PRESCALER == 64 + REG_TCCR0B |= TIMER0_PRESCALER_64; + #else + #error Unsupported value of TIMER_PRESCALER + #endif + + TCNT0 = 0x00; /* Initialization of Timer/Counter */ + REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ + + /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ + REG_TIMSK0 &= ~BV(TOIE0); + REG_TIMSK0 |= BV(BIT_OCIE0A); + + IRQ_RESTORE(flags); + } + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) + + void timer_hw_init(void) + { + cpu_flags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer overflow flag */ + REG_TIFR1 |= BV(TOV1); + + /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ + #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) + TCCR1A |= BV(WGM11); + TCCR1A &= ~BV(WGM10); + TCCR1B |= BV(WGM12) | BV(CS10); + TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); + /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ + #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) + TCCR1A |= BV(WGM10); + TCCR1A &= ~BV(WGM11); + TCCR1B |= BV(WGM12) | BV(CS10); + TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); + #else + #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS + #endif + + TCNT1 = 0x00; /* initialization of Timer/Counter */ + + /* Enable timer interrupt: Timer/Counter1 Overflow */ + REG_TIMSK1 |= BV(TOIE1); + + IRQ_RESTORE(flags); + } + +#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) + void timer_hw_init(void) + { + cpu_flags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer flags */ + REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); + + /* Setup Timer/Counter interrupt */ + REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to + REG_TCCR2B = 0; // ensure correct initialization. + + REG_TCCR2A = BV(WGM21); + #if TIMER_PRESCALER == 64 + REG_TCCR2B |= TIMER2_PRESCALER_64; + #else + #error Unsupported value of TIMER_PRESCALER + #endif + + /* Clear on Compare match & prescaler = 64, internal sys clock. + When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ + TCNT2 = 0x00; /* initialization of Timer/Counter */ + REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */ + + /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ + REG_TIMSK2 &= ~BV(TOIE2); + REG_TIMSK2 |= BV(BIT_OCIE2A); + + IRQ_RESTORE(flags); + } + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) + + #if CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32 + #error For select target there is not TIMER_ON_OVERFLOW3, please select an other one. + #endif + + void timer_hw_init(void) + { + cpu_flags_t flags; + IRQ_SAVE_DISABLE(flags); + + /* Reset Timer overflow flag */ + REG_TIFR3 |= BV(TOV3); + + /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ + #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) + TCCR3A |= BV(WGM31); + TCCR3A &= ~BV(WGM30); + TCCR3B |= BV(WGM32) | BV(CS30); + TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); + /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ + #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) + TCCR3A |= BV(WGM30); + TCCR3A &= ~BV(WGM31); + TCCR3B |= BV(WGM32) | BV(CS30); + TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); + #else + #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS + #endif + + /* initialization of Timer/Counter */ + TCNT3 = 0x00; + + /* Enable timer interrupt: Timer/Counter3 Overflow */ + REG_TIMSK3 |= BV(TOIE3); + + IRQ_RESTORE(flags); + } + +#else + #error Unimplemented value for CONFIG_TIMER +#endif /* CONFIG_TIMER */ + diff --git a/bertos/cpu/avr/drv/timer_mega.h b/bertos/cpu/avr/drv/timer_mega.h new file mode 100644 index 00000000..2146620c --- /dev/null +++ b/bertos/cpu/avr/drv/timer_mega.h @@ -0,0 +1,173 @@ +/** + * \file + * + * + * \brief Low-level timer module for AVR (interface). + * + * \author Bernie Innocenti + * \author Francesco Sacchi + * \author Luca Ottaviano + * + */ + +#ifndef DRV_TIMER_AVR_H +#define DRV_TIMER_AVR_H + +#include /* CPU_FREQ */ + +#include "cfg/cfg_timer.h" /* CONFIG_TIMER */ +#include /* uint8_t */ +#include /* DIV_ROUND */ + +#include +#include + +/** + * \name Values for CONFIG_TIMER. + * + * Select which hardware timer interrupt to use for system clock and softtimers. + * \note The timer 1 overflow mode set the timer as a 24 kHz PWM. + * $WIZ$ timer_select = "TIMER_ON_OUTPUT_COMPARE0", "TIMER_ON_OVERFLOW1", "TIMER_ON_OUTPUT_COMPARE2", "TIMER_ON_OVERFLOW3", "TIMER_DEFAULT" + */ +#define TIMER_ON_OUTPUT_COMPARE0 1 +#define TIMER_ON_OVERFLOW1 2 +#define TIMER_ON_OUTPUT_COMPARE2 3 +#define TIMER_ON_OVERFLOW3 4 + +#define TIMER_DEFAULT TIMER_ON_OUTPUT_COMPARE0 ///< Default system timer + +/* + * Hardware dependent timer initialization. + */ +#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) + + #define TIMER_PRESCALER 64 + #define TIMER_HW_BITS 8 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMPA_vect) + #else + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER0_COMP_vect) + #endif + #define TIMER_TICKS_PER_SEC 1000 + #define TIMER_HW_CNT OCR_DIVISOR + + /// Type of time expressed in ticks of the hardware high-precision timer + typedef uint8_t hptime_t; + #define SIZEOF_HPTIME_T 1 + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT0; + } + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) + + #define TIMER_PRESCALER 1 + #define TIMER_HW_BITS 8 + /** This value is the maximum in overflow based timers. */ + #define TIMER_HW_CNT (1 << TIMER_HW_BITS) + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER1_OVF_vect) + #define TIMER_TICKS_PER_SEC DIV_ROUND(TIMER_HW_HPTICKS_PER_SEC, TIMER_HW_CNT) + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint16_t hptime_t; + #define SIZEOF_HPTIME_T 2 + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT1; + } + +#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) + + #define TIMER_PRESCALER 64 + #define TIMER_HW_BITS 8 + #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMPA_vect) + #else + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER2_COMP_vect) + #endif + #define TIMER_TICKS_PER_SEC 1000 + /** Value for OCR register in output-compare based timers. */ + #define TIMER_HW_CNT OCR_DIVISOR + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint8_t hptime_t; + #define SIZEOF_HPTIME_T 1 + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT2; + } + +#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) + + #define TIMER_PRESCALER 1 + #define TIMER_HW_BITS 8 + /** This value is the maximum in overflow based timers. */ + #define TIMER_HW_CNT (1 << TIMER_HW_BITS) + #define DEFINE_TIMER_ISR DECLARE_ISR_CONTEXT_SWITCH(TIMER3_OVF_vect) + #define TIMER_TICKS_PER_SEC DIV_ROUND(TIMER_HW_HPTICKS_PER_SEC, TIMER_HW_CNT) + + /// Type of time expressed in ticks of the hardware high precision timer + typedef uint16_t hptime_t; + #define SIZEOF_HPTIME_T 2 + + INLINE hptime_t timer_hw_hpread(void) + { + return TCNT3; + } + +#else + + #error Unimplemented value for CONFIG_TIMER +#endif /* CONFIG_TIMER */ + + +/** Frequency of the hardware high precision timer. */ +#define TIMER_HW_HPTICKS_PER_SEC DIV_ROUND(CPU_FREQ, TIMER_PRESCALER) + +/** + * System timer: additional division after the prescaler + * 12288000 / 64 / 192 (0..191) = 1 ms + */ +#define OCR_DIVISOR (DIV_ROUND(DIV_ROUND(CPU_FREQ, TIMER_PRESCALER), TIMER_TICKS_PER_SEC) - 1) + +/** Not needed, IRQ timer flag cleared automatically */ +#define timer_hw_irq() do {} while (0) + +/** Not needed, timer IRQ handler called only for timer source */ +#define timer_hw_triggered() (true) + +void timer_hw_init(void); + +#endif /* DRV_TIMER_AVR_H */