From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Fri, 18 Mar 2011 09:50:02 +0000 (+0000)
Subject: Add register definition for sam3 adc.
X-Git-Tag: 2.7.0~184
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=5d6e1feb6eb171345f5e36258bbc9763c580e1f9;p=bertos.git

Add register definition for sam3 adc.


git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4782 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/adc_cm3.h b/bertos/cpu/cortex-m3/drv/adc_cm3.h
index b9987e48..168a5da0 100644
--- a/bertos/cpu/cortex-m3/drv/adc_cm3.h
+++ b/bertos/cpu/cortex-m3/drv/adc_cm3.h
@@ -42,6 +42,8 @@
 	#include "adc_lm3s.h"
 #elif CPU_CM3_STM32
 	#include "adc_stm32.h"
+#elif CPU_CM3_SAM3X
+	#include "adc_sam3.h"
 /*#elif  Add other ARM families here */
 #else
 	#error Unknown CPU
diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 39712a0c..9437c611 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -169,6 +169,7 @@
 #include "sam3_wdt.h"
 #include "sam3_emac.h"
 #include "sam3_rstc.h"
+#include "sam3_adc.h"
 
 /**
  * U(S)ART I/O pins
diff --git a/bertos/cpu/cortex-m3/io/sam3_adc.h b/bertos/cpu/cortex-m3/io/sam3_adc.h
new file mode 100644
index 00000000..6f761b14
--- /dev/null
+++ b/bertos/cpu/cortex-m3/io/sam3_adc.h
@@ -0,0 +1,201 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Daniele Basile <asterix@develer.com>
+ *
+ * SAM3 Analog to Digital Converter.
+ *
+ */
+
+
+#ifndef SAM3_ADC_H
+#define SAM3_ADC_H
+
+/** ADC registers base. */
+#define ADC_BASE                0x400C0000
+
+/**
+ * ADC control register
+ * \{
+ */
+#define ADC_CR_OFF              0x00000000     ///< Control register offeset.
+#define ADC_CR          (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
+#define ADC_SWRST                        0      ///< Software reset.
+#define ADC_START                        1      ///< Start conversion.
+/* \} */
+
+/**
+ * ADC mode register
+ * \{
+ */
+#define ADC_MR_OFF              0x00000004     ///< Mode register offeset.
+#define ADC_MR          (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
+#define ADC_TRGEN                        0     ///< Trigger enable.
+
+#define ADC_TRGSEL_TIOA0         0x00000000    ///< TIOA output of the timer counter channel 0.
+#define ADC_TRGSEL_TIOA1         0x00000002    ///< TIOA output of the timer counter channel 1.
+#define ADC_TRGSEL_TIOA2         0x00000004    ///< TIOA output of the timer counter channel 2.
+#define ADC_TRGSEL_PWM0           0x0000000A    ///< PWM Event Line 0.
+#define ADC_TRGSEL_PWM1           0x0000000C    ///< PWM Event Line 1.
+
+#define ADC_LOWRES                        4   ///< Resolution 0: 12-bit, 1: 10-bit.
+#define ADC_SLEEP                         5   ///< Sleep mode.
+
+
+/**
+ * Prescaler rate selection.
+ * ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
+ */
+#define ADC_PRESCALER_MASK       0x0000FF00   ///< Prescaler rate selection mask.
+#define ADC_PRESCALER_SHIFT               8   ///< Prescale  rate selection shift.
+
+/**
+ * Start up timer.
+ */
+#define ADC_STARTUP_MASK         0x000F0000   ///< Start up timer mask.
+#define ADC_STARTUP_SHIFT                16   ///< Start up timer shift.
+#define ADC_SUT0                          0   ///< 0 period of ADCClock.
+#define ADC_SUT1                          1   ///< 8 period of ADCClock.
+#define ADC_SUT2                          2   ///< 16 period of ADCClock.
+#define ADC_SUT3                          3   ///< 24 period of ADCClock.
+#define ADC_SUT4                          4   ///< 64 period of ADCClock.
+#define ADC_SUT5                          5   ///< 80 period of ADCClock.
+#define ADC_SUT6                          6   ///< 96 period of ADCClock.
+#define ADC_SUT7                          7   ///< 112 period of ADCClock.
+#define ADC_SUT8                          8   ///< 512 period of ADCClock.
+#define ADC_SUT9                          9   ///< 576 period of ADCClock.
+#define ADC_SUT10                         10   ///< 640 period of ADCClock.
+#define ADC_SUT11                         11   ///< 704 period of ADCClock.
+#define ADC_SUT12                         12   ///< 768 period of ADCClock.
+#define ADC_SUT13                         13   ///< 832 period of ADCClock.
+#define ADC_SUT14                         14   ///< 832 period of ADCClock.
+#define ADC_SUT15                         15   ///< 896 period of ADCClock.
+#define ADC_SUT16                         16   ///< 960 period of ADCClock.
+
+
+/**
+ * Sample & hold time.
+  */
+#define ADC_SHTIME_MASK          0x0F000000   ///< Sample & hold time mask.
+#define ADC_SHTIME_SHIFT                 20   ///< Sample & hold time shift.
+#define ADC_AST3                          0   ///< 3 period of ADCClock
+#define ADC_AST5                          1   ///< 5 period of ADCClock
+#define ADC_AST9                          2   ///< 9 period of ADCClock
+#define ADC_AST17                         3   ///< 17 period of ADCClock
+/* \} */
+
+/**
+ * ADC channel enable register
+ */
+#define ADC_CHER_OFF             0x00000010     ///< Channel enable register offeset.
+#define ADC_CHER          (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///<  Channel enable register address.
+
+/**
+ * ADC channel disable register
+ */
+#define ADC_CHDR_OFF             0x00000014     ///< Channel disable register offeset.
+#define ADC_CHDR          (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///<  Channel disable register address.
+
+/**
+ * ADC channel status register
+ */
+#define ADC_CHSR_OFF             0x00000018     ///< Channel status register offeset.
+#define ADC_CHSR          (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///<  Channel status register address.
+
+#define ADC_CH_MASK              0x000000FF    ///< Channel mask.
+#define ADC_CH0                           0    ///< Channel 0
+#define ADC_CH1                           1    ///< Channel 1
+#define ADC_CH2                           2    ///< Channel 2
+#define ADC_CH3                           3    ///< Channel 3
+#define ADC_CH4                           4    ///< Channel 4
+#define ADC_CH5                           5    ///< Channel 5
+#define ADC_CH6                           6    ///< Channel 6
+#define ADC_CH7                           7    ///< Channel 7
+
+/**
+ * ADC Interrupt enable register.
+ */
+#define ADC_IER_OFF              0x00000024     ///< Interrupt enable register offeset.
+#define ADC_IER          (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///<  Interrupt enable register.
+
+/**
+ * ADC Interrupt disable register.
+ */
+#define ADC_IDR_OFF              0x00000028     ///< Interrupt disable register offeset.
+#define ADC_IDR          (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///<  Interrupt disable register.
+
+/**
+ * ADC Interrupt mask register.
+ */
+#define ADC_IMR_OFF              0x0000002C     ///< Interrupt mask register offeset.
+#define ADC_IMR          (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///<  Interrupt mask register.
+
+/**
+ * ADC Interrupt status register.
+ */
+#define ADC_ISR_OFF              0x00000030     ///< Interrupt status register offeset.
+#define ADC_ISR          (*((reg32_t *)(ADC_BASE + ADC_ISR_OFF))) ///<  Interrupt status register.
+
+#define ADC_EOC_MASK             0x000000FF    ///< End of converison mask.
+#define ADC_EOC0                          0    ///< End of conversion channel 0.
+#define ADC_EOC1                          1    ///< End of conversion channel 1.
+#define ADC_EOC2                          2    ///< End of conversion channel 2.
+#define ADC_EOC3                          3    ///< End of conversion channel 3.
+#define ADC_EOC4                          4    ///< End of conversion channel 4.
+#define ADC_EOC5                          5    ///< End of conversion channel 5.
+#define ADC_EOC6                          6    ///< End of conversion channel 6.
+#define ADC_EOC7                          7    ///< End of conversion channel 7.
+
+#define ADC_OVRE0                         8    ///< Overrun error channel 0.
+#define ADC_OVRE1                         9    ///< Overrun error channel 1.
+#define ADC_OVRE2                        10    ///< Overrun error channel 2.
+#define ADC_OVRE3                        11    ///< Overrun error channel 3.
+#define ADC_OVRE4                        12    ///< Overrun error channel 4.
+#define ADC_OVRE5                        13    ///< Overrun error channel 5.
+#define ADC_OVRE6                        14    ///< Overrun error channel 6.
+#define ADC_OVRE7                        15    ///< Overrun error channel 7.
+
+#define ADC_DRDY                         24    ///< Data ready.
+#define ADC_GOVRE                        25    ///< General overrun error.
+#define ADC_COMPE                        26    ///< Comparition event interrupt mask.
+#define ADC_ENDRX                        27    ///< End of RX buffer.
+#define ADC_RXBUFF                       28    ///< Rx buffer full.
+
+/**
+ * ADC last convert data register.
+ */
+#define ADC_LCDR_OFF             0x00000020     ///< Last converted data register offeset.
+#define ADC_LCDR          (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register.
+#define ADC_LDATA         (ADC_LCDR & 0xFFF)  ///< Last data converted register.
+#define ADC_CHNB          ((ADC_LCDR & 0xF000) >> 12) ///< Channel number.
+
+#endif /* SAM3_ADC_H */