From: batt <batt@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Fri, 5 Oct 2007 17:12:06 +0000 (+0000)
Subject: Fix ARM IRQ macros (untested).
X-Git-Tag: 1.0.0~412
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=5f716eb9939ef669ff690eafc2550d85d6b04447;p=bertos.git

Fix ARM IRQ macros (untested).


git-svn-id: https://src.develer.com/svnoss/bertos/trunk@829 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/cfg/cpu.h b/cfg/cpu.h
index 23d0ddf1..ff277d62 100755
--- a/cfg/cpu.h
+++ b/cfg/cpu.h
@@ -94,8 +94,8 @@
 	#define CPU_REG_BITS           32
 	#define CPU_REGS_CNT           16
 	#define CPU_SAVED_REGS_CNT     FIXME
-	#define CPU_STACK_GROWS_UPWARD 0  //FIXME
-	#define CPU_SP_ON_EMPTY_SLOT   0  //FIXME
+	#define CPU_STACK_GROWS_UPWARD 0
+	#define CPU_SP_ON_EMPTY_SLOT   0
 	#define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
 	#define CPU_HARVARD            0
 
@@ -135,6 +135,7 @@
 	#else /* !__IAR_SYSTEMS_ICC__ */
 
 		#warning "IRQ_ macros need testing!"
+		#warning "Test now or die :-)"
 
 		#define NOP         asm volatile ("mov r0,r0" ::)
 
@@ -142,9 +143,9 @@
 		do { \
 			asm volatile ( \
 				"mrs r0, cpsr\n\t" \
-				"orr r0, r0, #0xb0\n\t" \
-				"msr cpsr, r0" \
-				:: \
+				"orr r0, r0, #0xc0\n\t" \
+				"msr cpsr_c, r0" \
+				::: "r0" \
 			); \
 		} while (0)
 
@@ -152,19 +153,18 @@
 		do { \
 			asm volatile ( \
 				"mrs r0, cpsr\n\t" \
-				"bic r0, r0, #0xb0\n\t" \
-				"msr cpsr, r0" \
-				:: \
+				"bic r0, r0, #0xc0\n\t" \
+				"msr cpsr_c, r0" \
+				::: "r0" \
 			); \
 		} while (0)
 
 		#define IRQ_SAVE_DISABLE(x) \
 		do { \
 			asm volatile ( \
-				"mrs r0, cpsr\n\t" \
-				"mov %0, r0\n\t" \
-				"orr r0, r0, #0xb0\n\t" \
-				"msr cpsr, r0" \
+				"mrs %0, cpsr\n\t" \
+				"orr r0, %0, #0xc0\n\t" \
+				"msr cpsr_c, r0" \
 				: "=r" (x) \
 				: /* no inputs */ \
 				: "r0" \
@@ -174,11 +174,9 @@
 		#define IRQ_RESTORE(x) \
 		do { \
 			asm volatile ( \
-				"mov r0, %0\n\t" \
-				"msr cpsr, r0" \
+				"msr cpsr_c, %0" \
 				: /* no outputs */ \
 				: "r" (x) \
-				: "r0" \
 			); \
 		} while (0)
 
@@ -186,16 +184,14 @@
 		({ \
 			uint32_t sreg; \
 			asm volatile ( \
-				"mrs r0, cpsr\n\t" \
-				"mov %0, r0" \
+				"mrs %0, cpsr\n\t" \
 				: "=r" (sreg) \
 				: /* no inputs */ \
-				: "r0" \
 			); \
-			(bool)(sreg & 0xb0); \
+			!((sreg & 0xc0) == 0xc0); \
 		})
 
-	#endif /* __IAR_SYSTEMS_ICC_ */
+	#endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC
 	#define NOP                 asm volatile ("nop" ::)
diff --git a/cfg/cpu_detect.h b/cfg/cpu_detect.h
index 75c6f13a..615f952d 100755
--- a/cfg/cpu_detect.h
+++ b/cfg/cpu_detect.h
@@ -21,6 +21,7 @@
 
 #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \
 	&& !defined(__ARM4TM__) /* IAR: if not ARM assume I196 */
+	#warning Assuming CPU is I196
 	#define CPU_I196		1
 	#define CPU_ID                  i196
 #else