From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Wed, 28 Jul 2010 15:40:25 +0000 (+0000)
Subject: Refactor to works with new api. Clean up.
X-Git-Tag: 2.6.0~288^2~12
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=5f71a5cfc0bd0ef139b754c737c10a299d9110bd;p=bertos.git

Refactor to works with new api. Clean up.

git-svn-id: https://src.develer.com/svnoss/bertos/branches/i2c@4083 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/i2c_lm3s.c b/bertos/cpu/cortex-m3/drv/i2c_lm3s.c
index b0590ebe..c74a667e 100644
--- a/bertos/cpu/cortex-m3/drv/i2c_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/i2c_lm3s.c
@@ -56,225 +56,227 @@
 #include <drv/gpio_lm3s.h>
 #include <drv/clock_lm3s.h>
 
-/*
- *
- */
-#if 0
-	/* I2C 0 */
-	#define I2C                        I2C0_MASTER_BASE
-	#define SYSCTL_RCGC1_I2C           SYSCTL_RCGC1_I2C0
-	#define SYSCTL_RCGC2_GPIO          SYSCTL_RCGC2_GPIOB
-	#define GPIO_I2C_SCL_PIN           GPIO_I2C0_SCL_PIN
-	#define GPIO_I2C_SDA_PIN           GPIO_I2C0_SDA_PIN
-	#define GPIO_PORT_BASE             GPIO_PORTB_BASE
-#else
-	/* I2C 1 */
-	#define I2C                        I2C1_MASTER_BASE
-	#define SYSCTL_RCGC1_I2C           SYSCTL_RCGC1_I2C1
-	#define SYSCTL_RCGC2_GPIO          SYSCTL_RCGC2_GPIOA
-	#define GPIO_I2C_SCL_PIN           GPIO_I2C1_SCL_PIN
-	#define GPIO_I2C_SDA_PIN           GPIO_I2C1_SDA_PIN
-	#define GPIO_PORT_BASE             GPIO_PORTA_BASE
-#endif
-
 
-/**
- * Send START condition and select slave for write.
- * \c id is the device id comprehensive of address left shifted by 1.
- * The LSB of \c id is ignored and reset to 0 for write operation.
- *
- * \return true on success, false otherwise.
- */
-bool i2c_builtin_start_w(uint8_t id)
+struct I2cHardware
 {
-	HWREG(I2C + I2C_O_MSA) = id & ~BV(0);
-	return true;
-}
-
-
-/**
- * Send START condition and select slave for read.
- * \c id is the device id comprehensive of address left shifted by 1.
- * The LSB of \c id is ignored and set to 1 for read operation.
- *
- * \return true on success, false otherwise.
- */
-bool i2c_builtin_start_r(uint8_t id)
+	uint32_t base;
+	uint32_t sys_cntl;
+	uint32_t sys_gpio;
+	uint32_t pin_mask;
+	uint32_t gpio_base;
+	bool first_send;
+};
+
+static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr)
 {
-	HWREG(I2C + I2C_O_MSA) = id | BV(0);
-	return true;
-}
-
+	i2c->hw->first_send = true;
 
-void i2c_builtin_stop(void)
-{
+	if (I2C_TEST_START(i2c->flags) == I2C_START_W)
+		HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0);
+	else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
+		HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0);
 }
 
-
-bool i2c_builtin_put(const uint8_t data)
-{
-	(void)data;
-	return true;
-}
-
-
-int i2c_builtin_get(bool ack)
-{
-	(void)ack;
-	return 0;
-}
-
-INLINE bool check_ack(uint32_t mode_mask)
+INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask)
 {
 	ticks_t start = timer_clock();
-	while ( HWREG(I2C + I2C_O_MCS) &  I2C_MCS_ADRACK )
+	while (1)
 	{
+		uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS);
+
 		if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
-		{
-			LOG_ERR("Timeout on I2C_START\n");
 			return false;
-		}
 
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_ERROR_STOP;
-
-		HWREG(I2C + I2C_O_MCS) = mode_mask;
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
+		if (status & I2C_MCS_ADRACK)
+		{
+			HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
+			continue;
+		}
+		else
+			break;
 	}
-
 	return true;
 }
 
-/*
- * With this function is allowed only the atomic write.
- */
-bool i2c_send(const void *_buf, size_t count)
+static void i2c_lm3s_put(I2c *i2c, const uint8_t data)
 {
-	const uint8_t *buf = (const uint8_t *)_buf;
-
-	HWREGB(I2C + I2C_O_MDR) = *buf++;
-
-	if (count == 1)
+	if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
 	{
-		count = 0;
+		HWREG(i2c->hw->base + I2C_O_MDR) = data;
+		HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
+		while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
 
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_SEND;
-
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
+		if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
+		{
+			LOG_ERR("Start timeout\n");
+			i2c->errors |= I2C_START_TIMEOUT;
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
+			return;
+		}
 
-		if ( !check_ack(I2C_MASTER_CMD_SINGLE_SEND) )
+		if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 		{
-			LOG_ERR("No single send start");
-			return false;
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
 		}
+
+		i2c->hw->first_send = false;
+		return;
 	}
 	else
 	{
-		count--;
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_START;
-
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
-
-		if ( !check_ack(I2C_MASTER_CMD_BURST_SEND_START) )
+		HWREG(i2c->hw->base + I2C_O_MDR) = data;
+		if (i2c->hw->first_send)
 		{
-			LOG_ERR("No burst send start");
-			return false;
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
+			while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+
+			if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
+			{
+				LOG_ERR("Start timeout\n");
+				i2c->errors |= I2C_START_TIMEOUT;
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+				while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+				return;
+			}
+
+			i2c->hw->first_send = false;
+			return;
 		}
-
-		while(count - 1)
+		else
 		{
-			HWREGB(I2C + I2C_O_MDR) = *buf++;
-			count--;
-			HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_CONT;
-			while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
-
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+
+			if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+			{
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+				while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+			}
 		}
-		HWREGB(I2C + I2C_O_MDR) = *buf++;
-		count--;
-
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_FINISH;
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
 	}
-
-	return true;
 }
 
-/**
- * In order to read bytes from the i2c we should make some tricks.
- */
-bool i2c_recv(void *_buf, size_t count)
+static uint8_t i2c_lm3s_get(I2c *i2c)
 {
-	uint8_t *buf = (uint8_t *)_buf;
-
-	if (count == 1)
-	{
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_RECEIVE;
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
-
-		if ( !check_ack(I2C_MASTER_CMD_SINGLE_RECEIVE) )
-			return false;
-
-		*buf++ = HWREG(I2C + I2C_O_MDR);
-		count = 0;
-	}
-	else
+	if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
 	{
+		HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
+		while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
 
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_START;
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
 
-		if ( !check_ack(I2C_MASTER_CMD_BURST_RECEIVE_START) )
-			return false;
+		if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
+		{
+			LOG_ERR("Start timeout\n");
+			i2c->errors |= I2C_START_TIMEOUT;
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+			return 0xFF;
+		}
 
-		*buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
-		count--;
+		uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
 
-		while(count - 1)
+		if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 		{
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+		}
 
-			HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_CONT;
-			while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
-
-			*buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
-			count--;
+		i2c->hw->first_send = false;
+		return data;
+	}
+	else
+	{
+		if (i2c->hw->first_send)
+		{
+			HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START;
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
+
+			if (!wait_addrAck(i2c, I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START))
+			{
+				LOG_ERR("Start timeout\n");
+				i2c->errors |= I2C_START_TIMEOUT;
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+				return 0xFF;
+			}
+
+			i2c->hw->first_send = false;
+			return HWREG(i2c->hw->base + I2C_O_MDR);
 		}
+		else
+		{
+			if (i2c->xfer_size > 1)
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN;
+			else
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
 
-		HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_FINISH;
-		while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
+			while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+			uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
 
-		*buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
-		count--;
-	}
+			if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+			{
+				HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
+				while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
+			}
 
-	return true;
+			return data;
+		}
+	}
+	return 0xFF;
 }
 
 MOD_DEFINE(i2c);
 
+static const I2cVT i2c_lm3s_vt =
+{
+	.start = i2c_lm3s_start,
+	.get = i2c_lm3s_get,
+	.put = i2c_lm3s_put,
+	.send = i2c_swSend,
+	.recv = i2c_swRecv,
+};
+
+struct I2cHardware i2c_lm3s_hw[] =
+{
+	{ /* I2C0 */
+		.base = I2C0_MASTER_BASE,
+		.sys_cntl = SYSCTL_RCGC1_I2C0,
+		.sys_gpio = SYSCTL_RCGC2_GPIOB,
+		.pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN),
+		.gpio_base = GPIO_PORTB_BASE,
+	},
+	{ /* I2C1 */
+		.base = I2C1_MASTER_BASE,
+		.sys_cntl = SYSCTL_RCGC1_I2C1,
+		.sys_gpio = SYSCTL_RCGC2_GPIOA,
+		.pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
+		.gpio_base = GPIO_PORTA_BASE,
+	},
+};
+
 /**
  * Initialize I2C module.
  */
-void i2c_builtin_init(void)
+void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
 {
+	i2c->hw = &i2c_lm3s_hw[dev];
+	i2c->vt = &i2c_lm3s_vt;
 
 	/* Enable the peripheral clock */
-	SYSCTL_RCGC1_R |= SYSCTL_RCGC1_I2C;
-	SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIO;
+	SYSCTL_RCGC1_R |= i2c->hw->sys_cntl;
+	SYSCTL_RCGC2_R |= i2c->hw->sys_gpio;
 
 	/* Configure GPIO pins to work as I2C pins */
-	lm3s_gpioPinConfig(GPIO_PORT_BASE, GPIO_I2C_SCL_PIN,
-		GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
-
-	lm3s_gpioPinConfig(GPIO_PORT_BASE, GPIO_I2C_SDA_PIN,
+	lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
 		GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
-
-
 	/*
 	 * Note: to set correctly the i2c speed we shold before enable the i2c
 	 * device and then set in master time period the correct value
 	 */
 
 	/* Enable i2c device */
-	HWREG(I2C + I2C_O_MCR) |= I2C_MCR_MFE;
+	HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE;
 
     /*
 	 * Compute the clock divider that achieves the fastest speed less than or
@@ -282,9 +284,7 @@ void i2c_builtin_init(void)
      * clock divider so that the resulting clock is always less than or equal
      * to the desired clock, never greater.
 	 */
-    HWREG(I2C + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * CONFIG_I2C_FREQ) - 1) / (2 * 10 * CONFIG_I2C_FREQ)) - 1;
-
-
+    HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1;
 
 	MOD_INIT(i2c);
 }
diff --git a/bertos/cpu/cortex-m3/drv/i2c_lm3s.h b/bertos/cpu/cortex-m3/drv/i2c_lm3s.h
new file mode 100644
index 00000000..8d08e681
--- /dev/null
+++ b/bertos/cpu/cortex-m3/drv/i2c_lm3s.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief Driver for the LM3S I2C (interface)
+ *
+ */
+
+#ifndef I2C_LM3S_H
+#define I2C_LM3S_H
+
+#include <drv/i2c.h>
+
+/**
+ * \name I2C devices enum
+ */
+enum
+{
+	I2C0,
+	I2C1,
+
+	I2C_CNT  /**< Number of serial ports */
+};
+
+void i2c_hw_init(I2c *i2c, int dev, uint32_t clock);
+void i2c_init_0(void);
+#endif /* I2C_LM3S_H */