From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Mon, 23 May 2011 16:37:20 +0000 (+0000)
Subject: Fix comment.
X-Git-Tag: 2.7.0~50
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=627bebb05f4fce9c4d5761090198f2ce87037f32;p=bertos.git

Fix comment.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4916 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/io/sam3_dacc.h b/bertos/cpu/cortex-m3/io/sam3_dacc.h
index 0848a3b2..562d5f49 100644
--- a/bertos/cpu/cortex-m3/io/sam3_dacc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -165,8 +165,8 @@
 /**
  * DACC Interrupt disable register
  */
-#define DACC_IMR_OFF             0x0000002C     ///< Interrupt disable register offeset.
-#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt disable register address.
+#define DACC_IMR_OFF             0x0000002C     ///< Interrupt mask register offeset.
+#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt mask register address.
 
 /**
  * DACC Interrupt status register
@@ -176,7 +176,7 @@
 
 #define DACC_TXRDY                        0     ///< Transmit ready interrupt
 #define DACC_EOC                          1     ///< End of conversion interrupt
-#define DACC_ENDTX                        2     ///< End of transmit buffer interrupt
+#define DACC_ENDTX                        2     ///< End of DMA Interrupt Flag
 #define DACC_TXBUFE                       3     ///< Transmit buffer empty interrupt