From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Tue, 27 Sep 2011 13:10:06 +0000 (+0000)
Subject: Manage the page writing on two banks. Move flash info in sam3 defines.
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=6970f4233dd70293d45f2df4406c581128e887dc;p=bertos.git

Manage the page writing on two banks. Move flash info in sam3 defines.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@5101 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/flash_sam3.c b/bertos/cpu/cortex-m3/drv/flash_sam3.c
index fdafc2ae..dfe68c5a 100644
--- a/bertos/cpu/cortex-m3/drv/flash_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/flash_sam3.c
@@ -61,11 +61,6 @@
 #include <string.h>
 
 
-#define FLASH_MEM_SIZE          0x80000UL ///< Internal flash memory size
-#define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
-#define FLASH_BANKS_NUM                 2 ///< Number of flash banks
-#define FLASH_BASE                    0x0
-
 struct FlashHardware
 {
 	uint8_t status;
@@ -79,7 +74,7 @@ struct FlashHardware
  *       executing code from flash while a writing process
  *       is in progress is forbidden.
  */
-RAM_FUNC NOINLINE static void write_page(uint32_t page)
+RAM_FUNC NOINLINE static void write_page_bank0(uint32_t page)
 {
 	// Send the 'write page' command
 	EEFC0_FCR = EEFC_FCR_FKEY | EFC_FCR_FCMD_EWP | EEFC_FCR_FARG(page);
@@ -91,6 +86,20 @@ RAM_FUNC NOINLINE static void write_page(uint32_t page)
 	}
 }
 
+#if FLASH_BANKS_NUM > 1
+RAM_FUNC NOINLINE static void write_page_bank1(uint32_t page)
+{
+	// Send the 'write page' command
+	EEFC1_FCR = EEFC_FCR_FKEY | EFC_FCR_FCMD_EWP | EEFC_FCR_FARG(page);
+
+	// Wait for the end of command
+	while(!(EEFC1_FSR & BV(EEFC_FSR_FRDY)))
+	{
+		//NOP;
+	}
+}
+#endif
+
 
 /**
  * Send write command.
@@ -104,10 +113,20 @@ INLINE void flash_sendWRcmd(uint32_t page)
 
 	LOG_INFO("Writing page %ld...\n", page);
 
-	IRQ_SAVE_DISABLE(flags);
-	write_page(page);
+	if (page > FLASH_PAGES_FOR_BANK)
+	{
+		page = page - FLASH_PAGES_FOR_BANK;
+		IRQ_SAVE_DISABLE(flags);
+		write_page_bank1(page);
+		IRQ_RESTORE(flags);
+	}
+	else
+	{
+		IRQ_SAVE_DISABLE(flags);
+		write_page_bank0(page);
+		IRQ_RESTORE(flags);
+	}
 
-	IRQ_RESTORE(flags);
 	LOG_INFO("Done\n");
 }
 
@@ -143,6 +162,7 @@ static bool flash_getStatus(struct KBlock *blk)
 	return true;
 }
 
+
 static size_t sam3_flash_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size)
 {
 	memcpy(buf, (void *)(idx * blk->blk_size +  FLASH_BASE + offset), size);
diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index b848667f..3d007d50 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -159,6 +159,7 @@
 #include "sam3_twi.h"
 #include "sam3_ssc.h"
 #include "sam3_hsmci.h"
+#include "sam3_chipid.h"
 
 /**
  * U(S)ART I/O pins
@@ -338,5 +339,17 @@
 	#error no ssc pins are defined for this cpu
 #endif
 
+
+#if CPU_CM3_SAM3X8
+	#define FLASH_MEM_SIZE          0x80000UL ///< Internal flash memory size
+	#define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+	#define FLASH_BANKS_NUM                 2 ///< Number of flash banks
+	#define FLASH_PAGES_FOR_BANK         1024 ///< Number pages for each bank
+	#define FLASH_BASE                    0x0
+#else
+	#error no internal flash info are defined for this cpu
+#endif
+
+
 /*\}*/
 #endif /* SAM3_H */