From: arighi Date: Mon, 29 Mar 2010 22:11:03 +0000 (+0000) Subject: lm3s1968: driver names refactoring. X-Git-Tag: 2.5.0~592 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=73a7e9cb144007905b5b9de8e3086423e79b6d71;p=bertos.git lm3s1968: driver names refactoring. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3316 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/drv/clock.c b/bertos/cpu/cortex-m3/drv/clock.c deleted file mode 100644 index f3d31ec5..00000000 --- a/bertos/cpu/cortex-m3/drv/clock.c +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * - * \brief LM3S1968 Clocking driver. - * - * \author Andrea Righi - */ - -#include -#include -#include "io/lm3s.h" -#include "clock.h" - -/* See: LM3S1968 Microcontroller DATASHEET, p.80 */ -static const unsigned long xtal_clk[] = -{ - 1000000, - 1843200, - 2000000, - 2457600, - 3579545, - 3686400, - 4000000, - 4096000, - 4915200, - 5000000, - 5120000, - 6000000, - 6144000, - 7372800, - 8000000, - 8192000, - 10000000, - 12000000, - 12288000, - 13560000, - 14318180, - 16000000, - 16384000, -}; - -/* Extract the main oscillator frequency from the RCC register */ -#define RCC_TO_CLK(rcc) \ - (xtal_clk[(((rcc) & SYSCTL_RCC_XTAL_MASK) >> \ - SYSCTL_RCC_XTAL_SHIFT)]) - -/* Extract the main oscillator frequency from the RCC register */ -#define RCC_TO_SYSDIV(rcc) \ - (((rcc & SYSCTL_RCC_SYSDIV_MASK) >> \ - SYSCTL_RCC_SYSDIV_SHIFT) + 1) - -/* - * Very small delay: each loop takes 3 cycles. - */ -INLINE void __delay(unsigned long iterations) -{ - asm volatile ( - "1: subs %0, #1\n\t" - " bne 1b\n\t" - : "=r"(iterations) : : "memory", "cc"); -} - -unsigned long clock_get_rate(void) -{ - unsigned long rcc, clk; - - rcc = HWREG(SYSCTL_RCC); - - /* Get the main oscillator frequency */ - clk = RCC_TO_CLK(rcc); - /* Apply system clock divider */ - clk /= RCC_TO_SYSDIV(rcc); - - return clk; -} - -void clock_set_rate(void) -{ - reg32_t rcc, rcc2; - unsigned long clk; - int i; - - rcc = HWREG(SYSCTL_RCC); - rcc2 = HWREG(SYSCTL_RCC2); - - /* - * Step #1: bypass the PLL and system clock divider by setting the - * BYPASS bit and clearing the USESYS bit in the RCC register. This - * configures the system to run off a “raw” clock source (using the - * main oscillator or internal oscillator) and allows for the new PLL - * configuration to be validated before switching the system clock to - * the PLL. - */ - rcc |= SYSCTL_RCC_BYPASS; - rcc &= ~SYSCTL_RCC_USESYSDIV; - rcc2 |= SYSCTL_RCC2_BYPASS2; - - /* Write back RCC/RCC2 registers */ - HWREG(SYSCTL_RCC) = rcc; - HWREG(SYSCTL_RCC) = rcc2; - - /* - * Step #2: select the crystal value (XTAL) and oscillator source - * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL - * field automatically pulls valid PLL configuration data for the - * appropriate crystal, and clearing the PWRDN bit powers and enables - * the PLL and its output. - */ - - /* Enable the main oscillator first. */ - rcc &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); - rcc |= SYSCTL_RCC_IOSCDIS; - - /* Do not override RCC register fields */ - rcc2 &= ~SYSCTL_RCC2_USERCC2; - - rcc &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_PWRDN); - rcc |= XTAL_FREQ | SYSCTL_RCC_OSCSRC_MAIN; - - /* Clear the PLL lock interrupt. */ - HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; - - HWREG(SYSCTL_RCC) = rcc; - - __delay(16); - - /* - * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and - * set the USESYS bit in RCC. The SYSDIV field determines the system - * frequency for the microcontroller. - */ - rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV); - - /* - * Try to evaluate the correct SYSDIV value depending on the desired - * CPU frequency. - */ - clk = RCC_TO_CLK(rcc); - for (i = 0; i < 16; i++) - { - clk = clk / (i + 1); - if (CPU_FREQ >= clk) - break; - } - if (i) - { - rcc |= SYSCTL_RCC_USESYSDIV; - rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT; - } - - /* - * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the - * Raw Interrupt Status (RIS) register. - */ - for (i = 0; i < 32768; i++) - if (HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) - break; - - /* - * Step #5: enable use of the PLL by clearing the BYPASS bit in - * RCC/RCC2. - */ - rcc &= ~SYSCTL_RCC_BYPASS; - - HWREG(SYSCTL_RCC) = rcc; - - __delay(16); -} diff --git a/bertos/cpu/cortex-m3/drv/clock.h b/bertos/cpu/cortex-m3/drv/clock.h deleted file mode 100644 index d4322cc2..00000000 --- a/bertos/cpu/cortex-m3/drv/clock.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * - * \brief Low-level clocking driver for LM3S1968. - * - * \author Andrea Righi - */ - -#ifndef DRV_LM3S1968_CLOCK_H -#define DRV_LM3S1968_CLOCK_H - -/* Crystal frequency attached to the main oscillator. */ -#define XTAL_FREQ SYSCTL_RCC_XTAL_8MHZ - -unsigned long clock_get_rate(void); -void clock_set_rate(void); - -#endif /* DRV_LM3S1968_CLOCK_H */ diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c new file mode 100644 index 00000000..b91b09bd --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c @@ -0,0 +1,159 @@ +/** + * \file + * + * + * \brief LM3S1968 Clocking driver. + * + * \author Andrea Righi + */ + +#include +#include +#include "io/lm3s.h" +#include "clock_lm3s.h" + +/* The PLL VCO frequency is 400 MHz */ +#define PLL_VCO 400000000UL + +/* Extract the system clock divisor from the RCC register */ +#define RCC_TO_DIV(rcc) \ + (((rcc & SYSCTL_RCC_SYSDIV_MASK) >> \ + SYSCTL_RCC_SYSDIV_SHIFT) + 1) + +/* + * Very small delay: each loop takes 3 cycles. + */ +INLINE void __delay(unsigned long iterations) +{ + asm volatile ( + "1: subs %0, #1\n\t" + " bne 1b\n\t" + : "=r"(iterations) : : "memory", "cc"); +} + +unsigned long clock_get_rate(void) +{ + reg32_t rcc = HWREG(SYSCTL_RCC); + + return rcc & SYSCTL_RCC_USESYSDIV ? + PLL_VCO / RCC_TO_DIV(rcc) : PLL_VCO; +} + +void clock_set_rate(void) +{ + reg32_t rcc, rcc2; + unsigned long clk; + int i; + + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); + + /* + * Step #1: bypass the PLL and system clock divider by setting the + * BYPASS bit and clearing the USESYS bit in the RCC register. This + * configures the system to run off a “raw” clock source (using the + * main oscillator or internal oscillator) and allows for the new PLL + * configuration to be validated before switching the system clock to + * the PLL. + */ + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2; + + /* Write back RCC/RCC2 registers */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC) = rcc2; + + /* + * Step #2: select the crystal value (XTAL) and oscillator source + * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL + * field automatically pulls valid PLL configuration data for the + * appropriate crystal, and clearing the PWRDN bit powers and enables + * the PLL and its output. + */ + + /* Enable the main oscillator first. */ + rcc &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + rcc |= SYSCTL_RCC_IOSCDIS; + + /* Do not override RCC register fields */ + rcc2 &= ~SYSCTL_RCC2_USERCC2; + + rcc &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_PWRDN); + rcc |= XTAL_FREQ | SYSCTL_RCC_OSCSRC_MAIN; + + /* Clear the PLL lock interrupt. */ + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC) = rcc2; + + __delay(16); + + /* + * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and + * set the USESYS bit in RCC. The SYSDIV field determines the system + * frequency for the microcontroller. + */ + rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV); + + /* + * Try to evaluate the correct SYSDIV value depending on the desired + * CPU frequency. + * + * NOTE: with BYPASS=0, SYSDIV < 3 are reserved values (see LM3S1968 + * Microcontroller DATASHEET, p.78). + */ + clk = PLL_VCO / 2; + for (i = 3; i < 16; i++) + if (CPU_FREQ >= (clk / (i + 1))) + break; + if (i) + rcc |= SYSCTL_RCC_USESYSDIV | (i << SYSCTL_RCC_SYSDIV_SHIFT); + + /* + * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the + * Raw Interrupt Status (RIS) register. + */ + for (i = 0; i < 32768; i++) + if (HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + break; + + /* + * Step #5: enable use of the PLL by clearing the BYPASS bit in + * RCC/RCC2. + */ + rcc &= ~SYSCTL_RCC_BYPASS; + + HWREG(SYSCTL_RCC) = rcc; + + __delay(16); +} diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.h b/bertos/cpu/cortex-m3/drv/clock_lm3s.h new file mode 100644 index 00000000..d4322cc2 --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.h @@ -0,0 +1,47 @@ +/** + * \file + * + * + * \brief Low-level clocking driver for LM3S1968. + * + * \author Andrea Righi + */ + +#ifndef DRV_LM3S1968_CLOCK_H +#define DRV_LM3S1968_CLOCK_H + +/* Crystal frequency attached to the main oscillator. */ +#define XTAL_FREQ SYSCTL_RCC_XTAL_8MHZ + +unsigned long clock_get_rate(void); +void clock_set_rate(void); + +#endif /* DRV_LM3S1968_CLOCK_H */ diff --git a/bertos/cpu/cortex-m3/drv/irq.c b/bertos/cpu/cortex-m3/drv/irq.c deleted file mode 100644 index 0da77c85..00000000 --- a/bertos/cpu/cortex-m3/drv/irq.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * - * \brief Cortex-M3 IRQ management. - * - * \author Andrea Righi - */ - -#include -#include -#include "io/lm3s.h" -#include "irq.h" - -static void (*irq_table[NUM_INTERRUPTS])(void) - __attribute__((section("vtable"))); - -static void unhandled_isr(void) -{ - /* Unhandled IRQ */ - ASSERT(0); -} - -void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler) -{ - cpu_flags_t flags; - - ASSERT(irq < NUM_INTERRUPTS); - - IRQ_SAVE_DISABLE(flags); - irq_table[irq] = handler; - IRQ_RESTORE(flags); -} - -void sysirq_freeHandler(sysirq_t irq) -{ - cpu_flags_t flags; - - ASSERT(irq < NUM_INTERRUPTS); - - IRQ_SAVE_DISABLE(flags); - irq_table[irq] = unhandled_isr; - IRQ_RESTORE(flags); -} - -void sysirq_init(void) -{ - cpu_flags_t flags; - int i; - - IRQ_SAVE_DISABLE(flags); - for (i = 0; i < NUM_INTERRUPTS; i++) - irq_table[i] = unhandled_isr; - - /* Update NVIC to point to the new vector table */ - HWREG(NVIC_VTABLE) = (size_t)irq_table; - IRQ_RESTORE(flags); -} diff --git a/bertos/cpu/cortex-m3/drv/irq.h b/bertos/cpu/cortex-m3/drv/irq.h deleted file mode 100644 index 1770ed1f..00000000 --- a/bertos/cpu/cortex-m3/drv/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * \file - * - * - * \brief IRQ management for the Cortex M3 processor. - * - * \author Andrea Righi - */ - -#ifndef DRV_CORTEX_M3_SYSIRQ_H -#define DRV_CORTEX_M3_SYSIRQ_H - -typedef void (*sysirq_handler_t)(void); -typedef unsigned int sysirq_t; - -void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler); -void sysirq_freeHandler(sysirq_t irq); - -void sysirq_init(void); - -#endif /* DRV_CORTEX_M3_SYSIRQ_H */ diff --git a/bertos/cpu/cortex-m3/drv/irq_lm3s.c b/bertos/cpu/cortex-m3/drv/irq_lm3s.c new file mode 100644 index 00000000..c1df5019 --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/irq_lm3s.c @@ -0,0 +1,86 @@ +/** + * \file + * + * + * \brief Cortex-M3 IRQ management. + * + * \author Andrea Righi + */ + +#include +#include +#include "io/lm3s.h" +#include "irq_lm3s.h" + +static void (*irq_table[NUM_INTERRUPTS])(void) + __attribute__((section("vtable"))); + +static void unhandled_isr(void) +{ + /* Unhandled IRQ */ + ASSERT(0); +} + +void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler) +{ + cpu_flags_t flags; + + ASSERT(irq < NUM_INTERRUPTS); + + IRQ_SAVE_DISABLE(flags); + irq_table[irq] = handler; + IRQ_RESTORE(flags); +} + +void sysirq_freeHandler(sysirq_t irq) +{ + cpu_flags_t flags; + + ASSERT(irq < NUM_INTERRUPTS); + + IRQ_SAVE_DISABLE(flags); + irq_table[irq] = unhandled_isr; + IRQ_RESTORE(flags); +} + +void sysirq_init(void) +{ + cpu_flags_t flags; + int i; + + IRQ_SAVE_DISABLE(flags); + for (i = 0; i < NUM_INTERRUPTS; i++) + irq_table[i] = unhandled_isr; + + /* Update NVIC to point to the new vector table */ + HWREG(NVIC_VTABLE) = (size_t)irq_table; + IRQ_RESTORE(flags); +} diff --git a/bertos/cpu/cortex-m3/drv/irq_lm3s.h b/bertos/cpu/cortex-m3/drv/irq_lm3s.h new file mode 100644 index 00000000..1770ed1f --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/irq_lm3s.h @@ -0,0 +1,49 @@ +/** + * \file + * + * + * \brief IRQ management for the Cortex M3 processor. + * + * \author Andrea Righi + */ + +#ifndef DRV_CORTEX_M3_SYSIRQ_H +#define DRV_CORTEX_M3_SYSIRQ_H + +typedef void (*sysirq_handler_t)(void); +typedef unsigned int sysirq_t; + +void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler); +void sysirq_freeHandler(sysirq_t irq); + +void sysirq_init(void); + +#endif /* DRV_CORTEX_M3_SYSIRQ_H */ diff --git a/bertos/cpu/cortex-m3/drv/timer.c b/bertos/cpu/cortex-m3/drv/timer.c deleted file mode 100644 index cfc7b1f5..00000000 --- a/bertos/cpu/cortex-m3/drv/timer.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * - * \brief Low-level timer driver for LM3S1968. - * - * \author Andrea Righi - */ - -#include -#include -#include "io/lm3s.h" - -#include "irq.h" -#include "timer.h" - -unsigned long ticks; - -INLINE void timer_hw_setPeriod(unsigned long period) -{ - ASSERT(period < (1 << 24)); - HWREG(NVIC_ST_RELOAD) = period; -} - -static void timer_hw_handler(void) -{ - ticks++; -} - -static void timer_hw_enable(void) -{ - HWREG(NVIC_ST_CTRL) |= - NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN; -} - -static void timer_hw_disable(void) -{ - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN); -} - -void timer_hw_init(void) -{ - timer_hw_setPeriod(1000000); - sysirq_setHandler(FAULT_SYSTICK, timer_hw_handler); - timer_hw_enable(); -} - -void timer_hw_exit(void) -{ - timer_hw_disable(); - sysirq_freeHandler(FAULT_SYSTICK); -} diff --git a/bertos/cpu/cortex-m3/drv/timer.h b/bertos/cpu/cortex-m3/drv/timer.h deleted file mode 100644 index 53fdd02f..00000000 --- a/bertos/cpu/cortex-m3/drv/timer.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * \file - * - * - * \brief Low-level timer driver for LM3S1968. - * - * \author Andrea Righi - */ - -#ifndef DRV_CORTEX_M3_TIMER_H -#define DRV_CORTEX_M3_TIMER_H - -void timer_hw_init(void); -void timer_hw_exit(void); - -#endif /* DRV_CORTEX_M3_TIMER_H */ diff --git a/bertos/cpu/cortex-m3/drv/timer_lm3s.c b/bertos/cpu/cortex-m3/drv/timer_lm3s.c new file mode 100644 index 00000000..2d6ee89a --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/timer_lm3s.c @@ -0,0 +1,80 @@ +/** + * \file + * + * + * \brief Low-level timer driver for LM3S1968. + * + * \author Andrea Righi + */ + +#include +#include +#include "io/lm3s.h" + +#include "irq_lm3s.h" +#include "timer_lm3s.h" + +unsigned long ticks; + +INLINE void timer_hw_setPeriod(unsigned long period) +{ + ASSERT(period < (1 << 24)); + HWREG(NVIC_ST_RELOAD) = period; +} + +static void timer_hw_handler(void) +{ + ticks++; +} + +static void timer_hw_enable(void) +{ + HWREG(NVIC_ST_CTRL) |= + NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN; +} + +static void timer_hw_disable(void) +{ + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN); +} + +void timer_hw_init(void) +{ + timer_hw_setPeriod(1000000); + sysirq_setHandler(FAULT_SYSTICK, timer_hw_handler); + timer_hw_enable(); +} + +void timer_hw_exit(void) +{ + timer_hw_disable(); + sysirq_freeHandler(FAULT_SYSTICK); +} diff --git a/bertos/cpu/cortex-m3/drv/timer_lm3s.h b/bertos/cpu/cortex-m3/drv/timer_lm3s.h new file mode 100644 index 00000000..53fdd02f --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/timer_lm3s.h @@ -0,0 +1,44 @@ +/** + * \file + * + * + * \brief Low-level timer driver for LM3S1968. + * + * \author Andrea Righi + */ + +#ifndef DRV_CORTEX_M3_TIMER_H +#define DRV_CORTEX_M3_TIMER_H + +void timer_hw_init(void); +void timer_hw_exit(void); + +#endif /* DRV_CORTEX_M3_TIMER_H */ diff --git a/bertos/cpu/cortex-m3/hw/startup_lm3s.c b/bertos/cpu/cortex-m3/hw/startup_lm3s.c index 5894dddd..279f14ce 100644 --- a/bertos/cpu/cortex-m3/hw/startup_lm3s.c +++ b/bertos/cpu/cortex-m3/hw/startup_lm3s.c @@ -37,8 +37,8 @@ #include #include -#include "drv/irq.h" -#include "drv/clock.h" +#include "drv/irq_lm3s.h" +#include "drv/clock_lm3s.h" #include "io/lm3s.h" extern size_t _etext, __data_start, __data_end, diff --git a/bertos/cpu/cortex-m3/io/lm3s.h b/bertos/cpu/cortex-m3/io/lm3s.h index 10fe02af..a7cf5a0e 100644 --- a/bertos/cpu/cortex-m3/io/lm3s.h +++ b/bertos/cpu/cortex-m3/io/lm3s.h @@ -46,6 +46,9 @@ #include "lm3s_ints.h" #include "lm3s_nvic.h" #include "lm3s_sysctl.h" + #include "lm3s_gpio.h" + #include "lm3s_memmap.h" + #include "lm3s_uart.h" #else #error Missing I/O definitions for CPU. #endif diff --git a/bertos/cpu/cortex-m3/io/lm3s_memmap.h b/bertos/cpu/cortex-m3/io/lm3s_memmap.h new file mode 100644 index 00000000..33993d9b --- /dev/null +++ b/bertos/cpu/cortex-m3/io/lm3s_memmap.h @@ -0,0 +1,120 @@ +/** + * \file + * + * + * \brief LM3S1968 memory map. + */ + +#ifndef LM3S_MEMMAP_H +#define LM3S_MEMMAP_H + +/** + * The following are defines for the base address of the memories and + * peripherals. + */ +/*\{*/ +#define FLASH_BASE 0x00000000 //< FLASH memory +#define SRAM_BASE 0x20000000 //< SRAM memory +#define WATCHDOG0_BASE 0x40000000 //< Watchdog0 +#define WATCHDOG1_BASE 0x40001000 //< Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 //< GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 //< GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 //< GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 //< GPIO Port D +#define SSI0_BASE 0x40008000 //< SSI0 +#define SSI1_BASE 0x40009000 //< SSI1 +#define UART0_BASE 0x4000C000 //< UART0 +#define UART1_BASE 0x4000D000 //< UART1 +#define UART2_BASE 0x4000E000 //< UART2 +#define I2C0_MASTER_BASE 0x40020000 //< I2C0 Master +#define I2C0_SLAVE_BASE 0x40020800 //< I2C0 Slave +#define I2C1_MASTER_BASE 0x40021000 //< I2C1 Master +#define I2C1_SLAVE_BASE 0x40021800 //< I2C1 Slave +#define GPIO_PORTE_BASE 0x40024000 //< GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 //< GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 //< GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 //< GPIO Port H +#define PWM_BASE 0x40028000 //< PWM +#define QEI0_BASE 0x4002C000 //< QEI0 +#define QEI1_BASE 0x4002D000 //< QEI1 +#define TIMER0_BASE 0x40030000 //< Timer0 +#define TIMER1_BASE 0x40031000 //< Timer1 +#define TIMER2_BASE 0x40032000 //< Timer2 +#define TIMER3_BASE 0x40033000 //< Timer3 +#define ADC0_BASE 0x40038000 //< ADC0 +#define ADC1_BASE 0x40039000 //< ADC1 +#define COMP_BASE 0x4003C000 //< Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 //< GPIO Port J +#define CAN0_BASE 0x40040000 //< CAN0 +#define CAN1_BASE 0x40041000 //< CAN1 +#define CAN2_BASE 0x40042000 //< CAN2 +#define ETH_BASE 0x40048000 //< Ethernet +#define MAC_BASE 0x40048000 //< Ethernet +#define USB0_BASE 0x40050000 //< USB 0 Controller +#define I2S0_BASE 0x40054000 //< I2S0 +#define GPIO_PORTA_AHB_BASE 0x40058000 //< GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 //< GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 //< GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 //< GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 //< GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 //< GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 //< GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 //< GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 //< GPIO Port J (high speed) +#define EPI0_BASE 0x400D0000 //< EPI0 +#define HIB_BASE 0x400FC000 //< Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 //< FLASH Controller +#define SYSCTL_BASE 0x400FE000 //< System Control +#define UDMA_BASE 0x400FF000 //< uDMA Controller +#define ITM_BASE 0xE0000000 //< Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 //< Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 //< FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 //< Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 //< Trace Port Interface Unit +/*\}*/ + +/** + * The following definitions are deprecated. + */ +/*\{*/ +#ifndef DEPRECATED +/*\}*/ + +#define WATCHDOG_BASE 0x40000000 //< Watchdog +#define SSI_BASE 0x40008000 //< SSI +#define I2C_MASTER_BASE 0x40020000 //< I2C Master +#define I2C_SLAVE_BASE 0x40020800 //< I2C Slave +#define QEI_BASE 0x4002C000 //< QEI +#define ADC_BASE 0x40038000 //< ADC + +#endif /* DEPRECATED */ + +#endif /* LM3S_MEMMAP_H */ diff --git a/bertos/cpu/cortex-m3/io/lm3s_types.h b/bertos/cpu/cortex-m3/io/lm3s_types.h index eede2c03..9bba5ff3 100644 --- a/bertos/cpu/cortex-m3/io/lm3s_types.h +++ b/bertos/cpu/cortex-m3/io/lm3s_types.h @@ -36,25 +36,24 @@ #ifndef LM3S_TYPES_H #define LM3S_TYPES_H +#include + /** * Macros for hardware access, both direct and via the bit-band region. */ /*\{*/ -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREG(x) (*((reg32_t *)(x))) +#define HWREGH(x) (*((reg16_t *)(x))) +#define HWREGB(x) (*((reg8_t *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((reg32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((reg32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((reg32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((reg32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((reg32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((reg32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) /*\}*/ /** diff --git a/examples/lm3s1968/lm3s1968.c b/examples/lm3s1968/lm3s1968.c index 6316ad18..68da7cda 100644 --- a/examples/lm3s1968/lm3s1968.c +++ b/examples/lm3s1968/lm3s1968.c @@ -37,7 +37,7 @@ #include #include "io/lm3s.h" -#include "drv/timer.h" +#include "drv/timer_lm3s.h" extern unsigned long ticks; diff --git a/examples/lm3s1968/lm3s1968.mk b/examples/lm3s1968/lm3s1968.mk index b55887e9..86a00b44 100644 --- a/examples/lm3s1968/lm3s1968.mk +++ b/examples/lm3s1968/lm3s1968.mk @@ -17,16 +17,16 @@ TRG += lm3s1968 lm3s1968_CSRC = \ examples/lm3s1968/lm3s1968.c \ - bertos/cpu/cortex-m3/drv/irq.c \ - bertos/cpu/cortex-m3/drv/timer.c \ - bertos/cpu/cortex-m3/drv/clock.c \ + bertos/cpu/cortex-m3/drv/irq_lm3s.c \ + bertos/cpu/cortex-m3/drv/timer_lm3s.c \ + bertos/cpu/cortex-m3/drv/clock_lm3s.c \ bertos/cpu/cortex-m3/hw/startup_lm3s.c # This is an hosted application lm3s1968_PREFIX = arm-none-eabi- lm3s1968_CPPAFLAGS = -O0 -g -gdwarf-2 -g -gen-debug -mthumb -fno-strict-aliasing -fwrapv -lm3s1968_CPPFLAGS = -O0 -D'ARCH=0' -D__ARM_LM3S1968__ -D'CPU_FREQ=(8000000L)' -g3 -gdwarf-2 -fverbose-asm -mthumb -Iexamples/lm3s1968 -Ibertos/cpu/cortex-m3 -fno-strict-aliasing -fwrapv +lm3s1968_CPPFLAGS = -O0 -D'ARCH=0' -D__ARM_LM3S1968__ -D'CPU_FREQ=(50000000L)' -g3 -gdwarf-2 -fverbose-asm -mthumb -Iexamples/lm3s1968 -Ibertos/cpu/cortex-m3 -fno-strict-aliasing -fwrapv lm3s1968_LDFLAGS = -nostartfiles -T bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld -Wl,--no-warn-mismatch -fno-strict-aliasing -fwrapv lm3s1968_CPU = cortex-m3