From: arighi Date: Fri, 9 Apr 2010 15:05:22 +0000 (+0000) Subject: CM3: trim the startup IRQ vector table. X-Git-Tag: 2.5.0~498 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=8d48fca0c6f7fd04286e1b6f73131a76ec035ad9;p=bertos.git CM3: trim the startup IRQ vector table. The startup IRQ vector table will be replaced by another one in RAM after the IRQ module initialization and the reset handler disables IRQ at the very beginning, so we can safely trim the rest of this table to reduce the memory footprint and save some space in flash. For example, for the lm3s1968 example: text data bss dec hex filename 23772 1036 18140 42948 a7c4 images/lm3s1968.elf text data bss dec hex filename 23596 1036 18140 42772 a714 images/lm3s1968.elf Moreover, make the vector IRQ table more generic (common for all the Cortex-M3-based boards). git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3410 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/hw/vectors_cm3.S b/bertos/cpu/cortex-m3/hw/vectors_cm3.S new file mode 100644 index 00000000..ec81c1a0 --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/vectors_cm3.S @@ -0,0 +1,73 @@ +/** + * \file + * + * + * \brief Cortex-M3 startup interrupt vector table + * + * \author Andrea Righi + */ + +.syntax unified +.thumb + +.text +.thumb_func +default_isr: + wfi + b default_isr + +.section .vectors,"ax",%progbits + +irq_vectors: + .word __msp_end /* Initial stack pointer */ + .word __init /* The reset handler */ + .word default_isr /* The NMI handler */ + .word default_isr /* The hard fault handler */ + .word default_isr /* The MPU fault handler */ + .word default_isr /* The bus fault handler */ + .word default_isr /* The usage fault handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word default_isr /* SVCall handler */ + .word default_isr /* Debug monitor handler */ + .word 0 /* Reserved */ + .word default_isr /* The PendSV handler */ + .word default_isr /* The SysTick handler */ +/* + * This IRQ vector table will be replaced by another one in RAM after the IRQ + * module initialization and the reset handler disables IRQ at the very + * beginning, so there is no chance to trigger the following IRQs. + * + * We can safely trim the rest of this table to reduce the memory footprint and + * save some space in flash. + */ diff --git a/bertos/cpu/cortex-m3/hw/vectors_lm3s.S b/bertos/cpu/cortex-m3/hw/vectors_lm3s.S deleted file mode 100644 index 45414374..00000000 --- a/bertos/cpu/cortex-m3/hw/vectors_lm3s.S +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * - * \brief LM3S1968 startup interrupt vector table - * - * \author Andrea Righi - */ - -.syntax unified -.thumb - -.text -.thumb_func -default_isr: - wfi - b default_isr - -.section .vectors,"ax",%progbits - -irq_vectors: - .word __msp_end /* Initial stack pointer */ - .word __init /* The reset handler */ - .word default_isr /* The NMI handler */ - .word default_isr /* The hard fault handler */ - .word default_isr /* The MPU fault handler */ - .word default_isr /* The bus fault handler */ - .word default_isr /* The usage fault handler */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word default_isr /* SVCall handler */ - .word default_isr /* Debug monitor handler */ - .word 0 /* Reserved */ - .word default_isr /* The PendSV handler */ - .word default_isr /* The SysTick handler */ - .word default_isr /* GPIO Port A */ - .word default_isr /* GPIO Port B */ - .word default_isr /* GPIO Port C */ - .word default_isr /* GPIO Port D */ - .word default_isr /* GPIO Port E */ - .word default_isr /* UART0 Rx and Tx */ - .word default_isr /* UART1 Rx and Tx */ - .word default_isr /* SSI0 Rx and Tx */ - .word default_isr /* I2C0 Master and Slave */ - .word default_isr /* PWM Fault */ - .word default_isr /* PWM Generator 0 */ - .word default_isr /* PWM Generator 1 */ - .word default_isr /* PWM Generator 2 */ - .word default_isr /* Quadrature Encoder 0 */ - .word default_isr /* ADC Sequence 0 */ - .word default_isr /* ADC Sequence 1 */ - .word default_isr /* ADC Sequence 2 */ - .word default_isr /* ADC Sequence 3 */ - .word default_isr /* Watchdog timer */ - .word default_isr /* Timer 0 subtimer A */ - .word default_isr /* Timer 0 subtimer B */ - .word default_isr /* Timer 1 subtimer A */ - .word default_isr /* Timer 1 subtimer B */ - .word default_isr /* Timer 2 subtimer A */ - .word default_isr /* Timer 2 subtimer B */ - .word default_isr /* Analog Comparator 0 */ - .word default_isr /* Analog Comparator 1 */ - .word default_isr /* Analog Comparator 2 */ - .word default_isr /* System Control (PLL, OSC, BO) */ - .word default_isr /* FLASH Control */ - .word default_isr /* GPIO Port F */ - .word default_isr /* GPIO Port G */ - .word default_isr /* GPIO Port H */ - .word default_isr /* UART2 Rx and Tx */ - .word default_isr /* SSI1 Rx and Tx */ - .word default_isr /* Timer 3 subtimer A */ - .word default_isr /* Timer 3 subtimer B */ - .word default_isr /* I2C1 Master and Slave */ - .word default_isr /* Quadrature Encoder 1 */ - .word default_isr /* CAN0 */ - .word default_isr /* CAN1 */ - .word default_isr /* CAN2 */ - .word default_isr /* Ethernet */ - .word default_isr /* Hibernate */ diff --git a/examples/lm3s1968/lm3s1968.mk b/examples/lm3s1968/lm3s1968.mk index 4d09c0ba..42f40954 100644 --- a/examples/lm3s1968/lm3s1968.mk +++ b/examples/lm3s1968/lm3s1968.mk @@ -49,7 +49,7 @@ lm3s1968_CSRC = \ bertos/cpu/cortex-m3/hw/init_lm3s.c lm3s1968_CPPASRC = \ - bertos/cpu/cortex-m3/hw/vectors_lm3s.S \ + bertos/cpu/cortex-m3/hw/vectors_cm3.S \ bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S \ bertos/cpu/cortex-m3/hw/crt_cm3.S \ #