From: arighi Date: Wed, 31 Mar 2010 16:54:12 +0000 (+0000) Subject: CM3: startup refactoring. X-Git-Tag: 2.5.0~542 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=a61181f8614fe8257dc21bf1762a380165932348;p=bertos.git CM3: startup refactoring. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3366 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/hw/crt_cm3.S b/bertos/cpu/cortex-m3/hw/crt_cm3.S new file mode 100644 index 00000000..a442bc59 --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/crt_cm3.S @@ -0,0 +1,96 @@ +/** + * \file + * + * + * \brief Cortex-M3 architecture's entry point + * + * \author Andrea Righi + */ + +.syntax unified +.thumb +.section .init, "ax", %progbits + +.weak __init +.set __init, __init0 + +.weak __init1 +.set __init1, __dummy_init + +.weak __init2 +.set __init2, __dummy_init + +.balign 2 +.thumb_func +__dummy_init: + bx lr + +/* + * Reset handler. + */ +.balign 2 +.thumb_func +__init0: + /* Disable IRQs */ + cpsid i + + /* Call the early hardware initialization routine */ + bl __init1 + + /* Copy the data segment initializers from flash to SRAM */ + ldr r0, =__text_end + ldr r1, =__data_start + ldr r2, =__data_end +data_loop: + cmp r1, r2 + ittt lo + ldrlo r3, [r0], #4 + strlo r3, [r1], #4 + blo data_loop + + /* Zero fill the bss segment */ + ldr r1, =__bss_start + ldr r2, =__bss_end + mov r0, #0 +bss_loop: + cmp r1, r2 + itt lo + strlo r0, [r1], #4 + blo bss_loop + + /* Call the hardware initialization routine */ + bl __init2 + + /* Call the application's entry point */ + bl main +end: + wfi + b end diff --git a/bertos/cpu/cortex-m3/hw/init_lm3s.c b/bertos/cpu/cortex-m3/hw/init_lm3s.c new file mode 100644 index 00000000..eaa05edf --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/init_lm3s.c @@ -0,0 +1,78 @@ +/** + * \file + * + * + * \brief Cortex-M3 architecture's entry point + * + * \author Andrea Righi + */ + +#include +#include +#include /* PAUSE */ +#include "drv/irq_lm3s.h" +#include "drv/clock_lm3s.h" +#include "io/lm3s.h" + +extern size_t __text_end, __data_start, __data_end, __bss_start, __bss_end; + +extern void __init2(void); + +/* Architecture's entry point */ +void __init2(void) +{ + /* + * PLL may not function properly at default LDO setting. + * + * Description: + * + * In designs that enable and use the PLL module, unstable device + * behavior may occur with the LDO set at its default of 2.5 volts or + * below (minimum of 2.25 volts). Designs that do not use the PLL + * module are not affected. + * + * Workaround: Prior to enabling the PLL module, it is recommended that + * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using + * the LDO Power Control (LDOPCTL) register. + * + * Silicon Revision Affected: A1, A2 + * + * See also: Stellaris LM3S1968 A2 Errata documentation. + */ + if (REVISION_IS_A1 | REVISION_IS_A2) + HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V; + + /* Set the appropriate clocking configuration */ + clock_set_rate(); + + /* Initialize IRQ vector table in RAM */ + sysirq_init(); +} diff --git a/bertos/cpu/cortex-m3/hw/startup_lm3s.c b/bertos/cpu/cortex-m3/hw/startup_lm3s.c deleted file mode 100644 index 2e985f64..00000000 --- a/bertos/cpu/cortex-m3/hw/startup_lm3s.c +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * - * \brief Cortex-M3 architecture's entry point - * - * \author Andrea Righi - */ - -#include -#include -#include "drv/irq_lm3s.h" -#include "drv/clock_lm3s.h" -#include "io/lm3s.h" - -extern size_t __text_end, __data_start, __data_end, - __bss_start, __bss_end, __stack_end; - -extern int main(void); - -/* Architecture's entry point */ -static void NORETURN NAKED _entry(void) -{ - size_t *src, *dst; - - /* - * PLL may not function properly at default LDO setting. - * - * Description: - * - * In designs that enable and use the PLL module, unstable device - * behavior may occur with the LDO set at its default of 2.5 volts or - * below (minimum of 2.25 volts). Designs that do not use the PLL - * module are not affected. - * - * Workaround: Prior to enabling the PLL module, it is recommended that - * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using - * the LDO Power Control (LDOPCTL) register. - * - * Silicon Revision Affected: A1, A2 - * - * See also: Stellaris LM3S1968 A2 Errata documentation. - */ - if (REVISION_IS_A1 | REVISION_IS_A2) - HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V; - - /* Set the appropriate clocking configuration */ - clock_set_rate(); - - /* Copy the data segment initializers from flash to SRAM */ - src = &__text_end; - for (dst = &__data_start; dst < &__data_end ; ) - *dst++ = *src++; - - /* Zero fill the bss segment */ - for (dst = &__bss_start; dst < &__bss_end ; ) - *dst++ = 0; - - /* Initialize IRQ vector table in RAM */ - sysirq_init(); - - /* Call the application's entry point */ - main(); - UNREACHABLE(); -} - -static void NORETURN NAKED default_isr(void) -{ - PAUSE; - UNREACHABLE(); -} - -/* Startup vector table */ -static void (* const irq_vectors[])(void) __attribute__ ((section(".vectors"))) = { - (void (*)(void))&__stack_end, /* Initial stack pointer */ - _entry, /* The reset handler */ - default_isr, /* The NMI handler */ - default_isr, /* The hard fault handler */ - default_isr, /* The MPU fault handler */ - default_isr, /* The bus fault handler */ - default_isr, /* The usage fault handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - default_isr, /* SVCall handler */ - default_isr, /* Debug monitor handler */ - 0, /* Reserved */ - default_isr, /* The PendSV handler */ - default_isr, /* The SysTick handler */ - default_isr, /* GPIO Port A */ - default_isr, /* GPIO Port B */ - default_isr, /* GPIO Port C */ - default_isr, /* GPIO Port D */ - default_isr, /* GPIO Port E */ - default_isr, /* UART0 Rx and Tx */ - default_isr, /* UART1 Rx and Tx */ - default_isr, /* SSI0 Rx and Tx */ - default_isr, /* I2C0 Master and Slave */ - default_isr, /* PWM Fault */ - default_isr, /* PWM Generator 0 */ - default_isr, /* PWM Generator 1 */ - default_isr, /* PWM Generator 2 */ - default_isr, /* Quadrature Encoder 0 */ - default_isr, /* ADC Sequence 0 */ - default_isr, /* ADC Sequence 1 */ - default_isr, /* ADC Sequence 2 */ - default_isr, /* ADC Sequence 3 */ - default_isr, /* Watchdog timer */ - default_isr, /* Timer 0 subtimer A */ - default_isr, /* Timer 0 subtimer B */ - default_isr, /* Timer 1 subtimer A */ - default_isr, /* Timer 1 subtimer B */ - default_isr, /* Timer 2 subtimer A */ - default_isr, /* Timer 2 subtimer B */ - default_isr, /* Analog Comparator 0 */ - default_isr, /* Analog Comparator 1 */ - default_isr, /* Analog Comparator 2 */ - default_isr, /* System Control (PLL, OSC, BO) */ - default_isr, /* FLASH Control */ - default_isr, /* GPIO Port F */ - default_isr, /* GPIO Port G */ - default_isr, /* GPIO Port H */ - default_isr, /* UART2 Rx and Tx */ - default_isr, /* SSI1 Rx and Tx */ - default_isr, /* Timer 3 subtimer A */ - default_isr, /* Timer 3 subtimer B */ - default_isr, /* I2C1 Master and Slave */ - default_isr, /* Quadrature Encoder 1 */ - default_isr, /* CAN0 */ - default_isr, /* CAN1 */ - default_isr, /* CAN2 */ - default_isr, /* Ethernet */ - default_isr /* Hibernate */ -}; diff --git a/bertos/cpu/cortex-m3/hw/vectors_lm3s.c b/bertos/cpu/cortex-m3/hw/vectors_lm3s.c new file mode 100644 index 00000000..5cf0a54d --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/vectors_lm3s.c @@ -0,0 +1,112 @@ +/** + * \file + * + * + * \brief LM3S1968 startup interrupt vector table + * + * \author Andrea Righi + */ + +#include +#include /* PAUSE, UNREACHABLE */ + +extern size_t __stack_end; +extern void __init(void); + +static void NORETURN NAKED default_isr(void) +{ + PAUSE; + UNREACHABLE(); +} + +static void (* const irq_vectors[])(void) __attribute__ ((section(".vectors"))) = +{ + (void (*)(void))&__stack_end, /* Initial stack pointer */ + __init, /* The reset handler */ + default_isr, /* The NMI handler */ + default_isr, /* The hard fault handler */ + default_isr, /* The MPU fault handler */ + default_isr, /* The bus fault handler */ + default_isr, /* The usage fault handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + default_isr, /* SVCall handler */ + default_isr, /* Debug monitor handler */ + 0, /* Reserved */ + default_isr, /* The PendSV handler */ + default_isr, /* The SysTick handler */ + default_isr, /* GPIO Port A */ + default_isr, /* GPIO Port B */ + default_isr, /* GPIO Port C */ + default_isr, /* GPIO Port D */ + default_isr, /* GPIO Port E */ + default_isr, /* UART0 Rx and Tx */ + default_isr, /* UART1 Rx and Tx */ + default_isr, /* SSI0 Rx and Tx */ + default_isr, /* I2C0 Master and Slave */ + default_isr, /* PWM Fault */ + default_isr, /* PWM Generator 0 */ + default_isr, /* PWM Generator 1 */ + default_isr, /* PWM Generator 2 */ + default_isr, /* Quadrature Encoder 0 */ + default_isr, /* ADC Sequence 0 */ + default_isr, /* ADC Sequence 1 */ + default_isr, /* ADC Sequence 2 */ + default_isr, /* ADC Sequence 3 */ + default_isr, /* Watchdog timer */ + default_isr, /* Timer 0 subtimer A */ + default_isr, /* Timer 0 subtimer B */ + default_isr, /* Timer 1 subtimer A */ + default_isr, /* Timer 1 subtimer B */ + default_isr, /* Timer 2 subtimer A */ + default_isr, /* Timer 2 subtimer B */ + default_isr, /* Analog Comparator 0 */ + default_isr, /* Analog Comparator 1 */ + default_isr, /* Analog Comparator 2 */ + default_isr, /* System Control (PLL, OSC, BO) */ + default_isr, /* FLASH Control */ + default_isr, /* GPIO Port F */ + default_isr, /* GPIO Port G */ + default_isr, /* GPIO Port H */ + default_isr, /* UART2 Rx and Tx */ + default_isr, /* SSI1 Rx and Tx */ + default_isr, /* Timer 3 subtimer A */ + default_isr, /* Timer 3 subtimer B */ + default_isr, /* I2C1 Master and Slave */ + default_isr, /* Quadrature Encoder 1 */ + default_isr, /* CAN0 */ + default_isr, /* CAN1 */ + default_isr, /* CAN2 */ + default_isr, /* Ethernet */ + default_isr /* Hibernate */ +}; diff --git a/examples/lm3s1968/lm3s1968.mk b/examples/lm3s1968/lm3s1968.mk index 453fddaf..db952703 100644 --- a/examples/lm3s1968/lm3s1968.mk +++ b/examples/lm3s1968/lm3s1968.mk @@ -33,10 +33,12 @@ lm3s1968_CSRC = \ bertos/cpu/cortex-m3/drv/timer_lm3s.c \ bertos/cpu/cortex-m3/drv/clock_lm3s.c \ bertos/cpu/cortex-m3/drv/kdebug_lm3s.c \ - bertos/cpu/cortex-m3/hw/startup_lm3s.c + bertos/cpu/cortex-m3/hw/vectors_lm3s.c \ + bertos/cpu/cortex-m3/hw/init_lm3s.c lm3s1968_CPPASRC = \ bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S \ + bertos/cpu/cortex-m3/hw/crt_cm3.S \ # # This is an hosted application @@ -56,7 +58,7 @@ lm3s1968_DEBUG_SCRIPT = bertos/prg_scripts/arm/debug.sh lm3s1968_STOPDEBUG_SCRIPT = bertos/prg_scripts/arm/stopopenocd.sh # Debug stuff -ifeq ($(demo_DEBUG),0) - demo_CFLAGS += -Os -fomit-frame-pointer - demo_CXXFLAGS += -Os -fomit-frame-pointer +ifeq ($(lm3s1968_DEBUG),0) + demo_CFLAGS += -O1 -fomit-frame-pointer + demo_CXXFLAGS += -O1 -fomit-frame-pointer endif