From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Mon, 28 Jun 2010 17:46:21 +0000 (+0000)
Subject: Fix sample time adc settings. Calibrate ADC when we init it.
X-Git-Tag: 2.6.0~348
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=b291e89733e9e820d6077bbb03d2068837040826;p=bertos.git

Fix sample time adc settings. Calibrate ADC when we init it.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3959 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/adc_stm32.c b/bertos/cpu/cortex-m3/drv/adc_stm32.c
index ed17ec10..ea07d88e 100644
--- a/bertos/cpu/cortex-m3/drv/adc_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/adc_stm32.c
@@ -150,7 +150,7 @@ uint16_t adc_hw_read(void)
 		adc_process = NULL;
 		return ret;
 	#else
-		/* Wait in polling until is done */
+		/* Wait in polling until conversion is done */
 		while (!(adc->SR & BV(SR_EOC)));
 
 		/* Return the last converted data */
@@ -163,8 +163,6 @@ uint16_t adc_hw_read(void)
  */
 void adc_hw_init(void)
 {
-	/* Enable clocking on AFIO */
-	RCC->APB2ENR |= RCC_APB2_AFIO;
 	RCC->APB2ENR |= (RCC_APB2_GPIOA | RCC_APB2_GPIOB | RCC_APB2_GPIOC);
 	RCC->APB2ENR |= RCC_APB2_ADC1;
 
@@ -175,6 +173,13 @@ void adc_hw_init(void)
 	adc->SQR2 = 0;
 	adc->SQR3 = 0;
 
+	/* Calibrate ADC */
+	adc->CR2 |= BV(CR2_RTSCAL);
+	adc->CR2 |= BV(CR2_CAL);
+
+	/* Wait in polling until calibration is done */
+	while (adc->CR2 & BV(CR2_CAL));
+
 	/*
 	 * Configure ADC
 	 *  - Regular mode
@@ -183,12 +188,28 @@ void adc_hw_init(void)
 	 */
 	adc->CR2 |= (BV(CR2_ADON) | ADC_EXTERNALTRIGCONV_NONE | BV(CR2_TSVREFE));
 
-	/* Set 17.1usec sampling time on channel 16 and 17 */
-	adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_16) |
-		(ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_17));
+	/* Set 17.1usec sampling time*/
+	adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH17) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH16) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH15) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH14) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH13) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH12) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH11) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH10));
+
+	adc->SMPR2 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH9) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH8) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH7) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH6) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH5) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH4) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH3) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH2) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH1) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH0));
 
 	#if CONFIG_KERN
 		adc_enable_irq();
 	#endif
-
 }
diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h
index b884b526..c34f3127 100644
--- a/bertos/cpu/cortex-m3/io/stm32_adc.h
+++ b/bertos/cpu/cortex-m3/io/stm32_adc.h
@@ -81,8 +81,8 @@
 #define ADC_CHANNEL_13                              ((uint8_t)0x0D)
 #define ADC_CHANNEL_14                              ((uint8_t)0x0E)
 #define ADC_CHANNEL_15                              ((uint8_t)0x0F)
-#define ADC_CHANNEL_16                              ((uint8_t)0X10)
-#define ADC_CHANNEL_17                              ((uint8_t)0X11)
+#define ADC_CHANNEL_16                              ((uint8_t)0x10)
+#define ADC_CHANNEL_17                              ((uint8_t)0x11)
 
 /* ADC sampling times */
 #define ADC_SAMPLETIME_1CYCLES5                    ((uint8_t)0x00)
@@ -247,6 +247,27 @@
 #define SR_JEOC                                        2
 #define SR_JSTRT                                       3
 #define SR_STRT                                        4
+
+/* ADC sample time */
+#define SMPR1_CH17                                    21
+#define SMPR1_CH16                                    18
+#define SMPR1_CH15                                    15
+#define SMPR1_CH14                                    12
+#define SMPR1_CH13                                     9
+#define SMPR1_CH12                                     6
+#define SMPR1_CH11                                     3
+#define SMPR1_CH10                                     0
+
+#define SMPR2_CH9                                     27
+#define SMPR2_CH8                                     24
+#define SMPR2_CH7                                     21
+#define SMPR2_CH6                                     18
+#define SMPR2_CH5                                     15
+#define SMPR2_CH4                                     12
+#define SMPR2_CH3                                      9
+#define SMPR2_CH2                                      6
+#define SMPR2_CH1                                      3
+#define SMPR2_CH0                                      0
 
 /* ADC registers Masks */
 #define CR1_ADC_CLEAR_MASK             ((uint32_t)0xFFF0FEFF)