From: aleph <aleph@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Sun, 13 Feb 2011 12:10:20 +0000 (+0000)
Subject: sam3: new cpu SAM3X8, add I/O base addresses, and update interrupt list
X-Git-Tag: 2.7.0~266
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=c49471ed35076929444a0a90899df4a6ee00a49a;p=bertos.git
sam3: new cpu SAM3X8, add I/O base addresses, and update interrupt list
git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4700 38d2e660-2303-0410-9eaa-f027e97ec537
---
diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 2b58220d..8e66d1e8 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -26,7 +26,7 @@
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
- * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
@@ -50,7 +50,7 @@
#define RTT_ID 3 ///< Real Time Timer (RTT)
#define WDT_ID 4 ///< Watchdog Timer (WDT)
#define PMC_ID 5 ///< Power Management Controller (PMC)
- #define EFC_ID 6 ///< Enhanced Flash Controller (EFC)
+ #define EEFC0_ID 6 ///< Enhanced Flash Controller
#define UART0_ID 8 ///< UART 0 (UART0)
#define UART1_ID 9 ///< UART 1 (UART1)
#define PIOA_ID 11 ///< Parallel I/O Controller A (PIOA)
@@ -70,6 +70,52 @@
#define ADC_ID 29 ///< Analog To Digital Converter (ADC)
#define DACC_ID 30 ///< Digital To Analog Converter (DACC)
#define PWM_ID 31 ///< Pulse Width Modulation (PWM)
+#elif CPU_CM3_SAM3X
+ #define SUPC_ID 0 ///< Supply Controller (SUPC)
+ #define RSTC_ID 1 ///< Reset Controller (RSTC)
+ #define RTC_ID 2 ///< Real Time Clock (RTC)
+ #define RTT_ID 3 ///< Real Time Timer (RTT)
+ #define WDT_ID 4 ///< Watchdog Timer (WDT)
+ #define PMC_ID 5 ///< Power Management Controller (PMC)
+ #define EEFC0_ID 6 ///< Enhanced Flash Controller
+ #define EEFC1_ID 7 ///< Enhanced Flash Controller
+ #define UART0_ID 8 ///< UART 0 (UART0)
+ #define SMC_SDRAMC_ID 9 ///< Satic memory controller / SDRAM controller
+ #define SDRAMC_ID 10 ///< Satic memory controller / SDRAM controller
+ #define PIOA_ID 11 ///< Parallel I/O Controller A
+ #define PIOB_ID 12 ///< Parallel I/O Controller B
+ #define PIOC_ID 13 ///< Parallel I/O Controller C
+ #define PIOD_ID 14 ///< Parallel I/O Controller D
+ #define PIOE_ID 15 ///< Parallel I/O Controller E
+ #define PIOF_ID 16 ///< Parallel I/O Controller F
+ #define US0_ID 17 ///< USART 0
+ #define US1_ID 18 ///< USART 1
+ #define US2_ID 19 ///< USART 2
+ #define US3_ID 20 ///< USART 3
+ #define HSMCI_ID 21 ///< High speed multimedia card interface
+ #define TWI0_ID 22 ///< Two Wire Interface 0
+ #define TWI1_ID 23 ///< Two Wire Interface 1
+ #define SPI0_ID 24 ///< Serial Peripheral Interface
+ #define SPI1_ID 25 ///< Serial Peripheral Interface
+ #define SSC_ID 26 ///< Synchronous serial controller
+ #define TC0_ID 27 ///< Timer/Counter 0
+ #define TC1_ID 28 ///< Timer/Counter 1
+ #define TC2_ID 29 ///< Timer/Counter 2
+ #define TC3_ID 30 ///< Timer/Counter 3
+ #define TC4_ID 31 ///< Timer/Counter 4
+ #define TC5_ID 32 ///< Timer/Counter 5
+ #define TC6_ID 33 ///< Timer/Counter 6
+ #define TC7_ID 34 ///< Timer/Counter 7
+ #define TC8_ID 35 ///< Timer/Counter 8
+ #define PWM_ID 36 ///< Pulse width modulation controller
+ #define ADC_ID 37 ///< ADC controller
+ #define DACC_ID 38 ///< DAC controller
+ #define DMAC_ID 39 ///< DMA controller
+ #define UOTGHS_ID 40 ///< USB OTG high speed
+ #define TRNG_ID 41 ///< True random number generator
+ #define EMAC_ID 42 ///< Ethernet MAC
+ #define CAN0_ID 43 ///< CAN controller 0
+ #define CAN1_ID 44 ///< CAN controller 1
#else
#error Peripheral IDs undefined
#endif
@@ -117,6 +163,9 @@
#if CPU_CM3_SAM3U
#define RXD0 11
#define TXD0 12
+#elif CPU_CM3_SAM3X
+ #define RXD0 8
+ #define TXD0 9
#else
#define RXD0 9
#define TXD0 10
@@ -133,6 +182,10 @@
#define SPI0_SPCK 15
#define SPI0_MOSI 14
#define SPI0_MISO 13
+#elif CPU_CM3_SAM3X
+ #define SPI0_SPCK 27
+ #define SPI0_MOSI 26
+ #define SPI0_MISO 25
#else
#define SPI0_SPCK 14
#define SPI0_MOSI 13
diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h
index 17b5be5e..44cae6a5 100644
--- a/bertos/cpu/cortex-m3/io/sam3_flash.h
+++ b/bertos/cpu/cortex-m3/io/sam3_flash.h
@@ -37,9 +37,15 @@
#define SAM3_FLASH_H
/**
- * EEFC base register address.
+ * EEFC base registers addresses.
*/
-#define EEFC_BASE 0x400E0A00
+/*\{*/
+#define EEFC0_BASE 0x400E0A00
+#ifdef CPU_CM3_SAM3X
+ #define EEFC1_BASE 0x400E0C00
+#endif
+/*\}*/
+
/**
* EFC register offsets.
@@ -55,10 +61,17 @@
* EEFC registers.
*/
/*\{*/
-#define EEFC_FMR (*((reg32_t *)(EEFC_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
-#define EEFC_FCR (*((reg32_t *)(EEFC_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
-#define EEFC_FSR (*((reg32_t *)(EEFC_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
-#define EEFC_FRR (*((reg32_t *)(EEFC_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
+#define EEFC0_FMR (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
+#define EEFC0_FCR (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
+#define EEFC0_FSR (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
+#define EEFC0_FRR (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
+
+#ifdef CPU_CM3_SAM3X
+ #define EEFC1_FMR (*((reg32_t *)(EEFC1_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
+ #define EEFC1_FCR (*((reg32_t *)(EEFC1_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
+ #define EEFC1_FSR (*((reg32_t *)(EEFC1_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
+ #define EEFC1_FRR (*((reg32_t *)(EEFC1_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
+#endif
/*\}*/
diff --git a/bertos/cpu/cortex-m3/io/sam3_ints.h b/bertos/cpu/cortex-m3/io/sam3_ints.h
index 4005ffe0..3c6bce85 100644
--- a/bertos/cpu/cortex-m3/io/sam3_ints.h
+++ b/bertos/cpu/cortex-m3/io/sam3_ints.h
@@ -26,7 +26,7 @@
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
- * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
@@ -57,39 +57,90 @@
/*\{*/
#define INT_PERIPH_BASE 16
-#define INT_SUPC (INT_PERIPH_BASE + SUPC_ID) ///< Supply Controller (SUPC)
-#define INT_RSTC (INT_PERIPH_BASE + RSTC_ID) ///< Reset Controller (RSTC)
-#define INT_RTC (INT_PERIPH_BASE + RTC_ID) ///< Real Time Clock (RTC)
-#define INT_RTT (INT_PERIPH_BASE + RTT_ID) ///< Real Time Timer (RTT)
-#define INT_WDT (INT_PERIPH_BASE + WDT_ID) ///< Watchdog Timer (WDT)
-#define INT_PMC (INT_PERIPH_BASE + PMC_ID) ///< Power Management Controller (PMC)
-#define INT_EFC (INT_PERIPH_BASE + EFC_ID) ///< Enhanced Flash Controller (EFC)
-#define INT_UART0 (INT_PERIPH_BASE + UART0_ID) ///< UART 0 (UART0)
-#define INT_UART1 (INT_PERIPH_BASE + UART1_ID) ///< UART 1 (UART1)
-#define INT_PIOA (INT_PERIPH_BASE + PIOA_ID) ///< Parallel I/O Controller A (PIOA)
-#define INT_PIOB (INT_PERIPH_BASE + PIOB_ID) ///< Parallel I/O Controller B (PIOB)
-#define INT_PIOC (INT_PERIPH_BASE + PIOC_ID) ///< Parallel I/O Controller C (PIOC)
-#define INT_US0 (INT_PERIPH_BASE + US0_ID) ///< USART 0 (USART0)
-#define INT_US1 (INT_PERIPH_BASE + US1_ID) ///< USART 1 (USART1)
-#define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID) ///< Two Wire Interface 0 (TWI0)
-#define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID) ///< Two Wire Interface 1 (TWI1)
-#define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID) ///< Serial Peripheral Interface (SPI)
-#define INT_TC0 (INT_PERIPH_BASE + TC0_ID) ///< Timer/Counter 0 (TC0)
-#define INT_TC1 (INT_PERIPH_BASE + TC1_ID) ///< Timer/Counter 1 (TC1)
-#define INT_TC2 (INT_PERIPH_BASE + TC2_ID) ///< Timer/Counter 2 (TC2)
-#define INT_TC3 (INT_PERIPH_BASE + TC3_ID) ///< Timer/Counter 3 (TC3)
-#define INT_TC4 (INT_PERIPH_BASE + TC4_ID) ///< Timer/Counter 4 (TC4)
-#define INT_TC5 (INT_PERIPH_BASE + TC5_ID) ///< Timer/Counter 5 (TC5)
-#define INT_ADC (INT_PERIPH_BASE + ADC_ID) ///< Analog To Digital Converter (ADC)
-#define INT_DACC (INT_PERIPH_BASE + DACC_ID) ///< Digital To Analog Converter (DACC)
-#define INT_PWM (INT_PERIPH_BASE + PWM_ID) ///< Pulse Width Modulation (PWM)
-/*\}*/
+#if CPU_CM3_SAM3N
+ #define INT_SUPC (INT_PERIPH_BASE + SUPC_ID)
+ #define INT_RSTC (INT_PERIPH_BASE + RSTC_ID)
+ #define INT_RTC (INT_PERIPH_BASE + RTC_ID)
+ #define INT_RTT (INT_PERIPH_BASE + RTT_ID)
+ #define INT_WDT (INT_PERIPH_BASE + WDT_ID)
+ #define INT_PMC (INT_PERIPH_BASE + PMC_ID)
+ #define INT_EFC (INT_PERIPH_BASE + EFC_ID)
+ #define INT_UART0 (INT_PERIPH_BASE + UART0_ID)
+ #define INT_UART1 (INT_PERIPH_BASE + UART1_ID)
+ #define INT_PIOA (INT_PERIPH_BASE + PIOA_ID)
+ #define INT_PIOB (INT_PERIPH_BASE + PIOB_ID)
+ #define INT_PIOC (INT_PERIPH_BASE + PIOC_ID)
+ #define INT_US0 (INT_PERIPH_BASE + US0_ID)
+ #define INT_US1 (INT_PERIPH_BASE + US1_ID)
+ #define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID)
+ #define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID)
+ #define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID)
+ #define INT_TC0 (INT_PERIPH_BASE + TC0_ID)
+ #define INT_TC1 (INT_PERIPH_BASE + TC1_ID)
+ #define INT_TC2 (INT_PERIPH_BASE + TC2_ID)
+ #define INT_TC3 (INT_PERIPH_BASE + TC3_ID)
+ #define INT_TC4 (INT_PERIPH_BASE + TC4_ID)
+ #define INT_TC5 (INT_PERIPH_BASE + TC5_ID)
+ #define INT_ADC (INT_PERIPH_BASE + ADC_ID)
+ #define INT_DACC (INT_PERIPH_BASE + DACC_ID)
+ #define INT_PWM (INT_PERIPH_BASE + PWM_ID)
-/**
- * Total number of interrupts.
- */
-/*\{*/
-#define NUM_INTERRUPTS 48
+ // Total number of interrupts.
+ #define NUM_INTERRUPTS 48
+
+#elif CPU_CM3_SAM3X
+ #define INT_SUPC (INT_PERIPH_BASE + SUPC_ID)
+ #define INT_RSTC (INT_PERIPH_BASE + RSTC_ID)
+ #define INT_RTC (INT_PERIPH_BASE + RTC_ID)
+ #define INT_RTT (INT_PERIPH_BASE + RTT_ID)
+ #define INT_WDT (INT_PERIPH_BASE + WDT_ID)
+ #define INT_PMC (INT_PERIPH_BASE + PMC_ID)
+ #define INT_EEFC0 (INT_PERIPH_BASE + EEFC0_ID)
+ #define INT_EEFC1 (INT_PERIPH_BASE + EEFC1_ID)
+ #define INT_UART0 (INT_PERIPH_BASE + UART0_ID)
+ #define INT_SMC_SDRAMC (INT_PERIPH_BASE + SMC_SDRAMC_ID)
+ #define INT_SDRAMC (INT_PERIPH_BASE + SDRAMC_ID)
+ #define INT_PIOA (INT_PERIPH_BASE + PIOA_ID)
+ #define INT_PIOB (INT_PERIPH_BASE + PIOB_ID)
+ #define INT_PIOC (INT_PERIPH_BASE + PIOC_ID)
+ #define INT_PIOD (INT_PERIPH_BASE + PIOD_ID)
+ #define INT_PIOE (INT_PERIPH_BASE + PIOE_ID)
+ #define INT_PIOF (INT_PERIPH_BASE + PIOF_ID)
+ #define INT_US0 (INT_PERIPH_BASE + US0_ID)
+ #define INT_US1 (INT_PERIPH_BASE + US1_ID)
+ #define INT_US2 (INT_PERIPH_BASE + US2_ID)
+ #define INT_US3 (INT_PERIPH_BASE + US3_ID)
+ #define INT_HSMCI (INT_PERIPH_BASE + HSMCI_ID)
+ #define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID)
+ #define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID)
+ #define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID)
+ #define INT_SPI1 (INT_PERIPH_BASE + SPI1_ID)
+ #define INT_SSC (INT_PERIPH_BASE + SSC_ID)
+ #define INT_TC0 (INT_PERIPH_BASE + TC0_ID)
+ #define INT_TC1 (INT_PERIPH_BASE + TC1_ID)
+ #define INT_TC2 (INT_PERIPH_BASE + TC2_ID)
+ #define INT_TC3 (INT_PERIPH_BASE + TC3_ID)
+ #define INT_TC4 (INT_PERIPH_BASE + TC4_ID)
+ #define INT_TC5 (INT_PERIPH_BASE + TC5_ID)
+ #define INT_TC6 (INT_PERIPH_BASE + TC6_ID)
+ #define INT_TC7 (INT_PERIPH_BASE + TC7_ID)
+ #define INT_TC8 (INT_PERIPH_BASE + TC8_ID)
+ #define INT_PWM (INT_PERIPH_BASE + PWM_ID)
+ #define INT_ADC (INT_PERIPH_BASE + ADC_ID)
+ #define INT_DACC (INT_PERIPH_BASE + DACC_ID)
+ #define INT_DMAC (INT_PERIPH_BASE + DMAC_ID)
+ #define INT_UOTGHS (INT_PERIPH_BASE + UOTGHS_ID)
+ #define INT_TRNG (INT_PERIPH_BASE + TRNG_ID)
+ #define INT_EMAC (INT_PERIPH_BASE + EMAC_ID)
+ #define INT_CAN0 (INT_PERIPH_BASE + CAN0_ID)
+ #define INT_CAN1 (INT_PERIPH_BASE + CAN1_ID)
+
+ // Total number of interrupts.
+ #define NUM_INTERRUPTS 61
+
+#else
+ #error Peripheral IDs undefined
+#endif
/*\}*/
#endif /* SAM3_INTS_H */
diff --git a/bertos/cpu/cortex-m3/io/sam3_pio.h b/bertos/cpu/cortex-m3/io/sam3_pio.h
index 443b873c..686efa72 100644
--- a/bertos/cpu/cortex-m3/io/sam3_pio.h
+++ b/bertos/cpu/cortex-m3/io/sam3_pio.h
@@ -79,6 +79,12 @@
#define PIOA_BASE 0x400E0E00
#define PIOB_BASE 0x400E1000
#define PIOC_BASE 0x400E1200
+
+#if CPU_CM3_SAM3X
+ #define PIOD_BASE 0x400E1400
+ #define PIOE_BASE 0x400E1600
+ #define PIOF_BASE 0x400E1800
+#endif
/*\}*/
/** PIO Register Offsets */
diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h
index b661c3b9..b0801c3d 100644
--- a/bertos/cpu/cortex-m3/io/sam3_pmc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h
@@ -37,7 +37,11 @@
#define SAM3_PMC_H
/** PMC registers base. */
-#define PMC_BASE 0x400E0400
+#if CPU_CM3_SAM3X
+ #define PMC_BASE 0x400E0600
+#else
+ #define PMC_BASE 0x400E0400
+#endif
/**
* PMC register offsets.
diff --git a/bertos/cpu/cortex-m3/io/sam3_spi.h b/bertos/cpu/cortex-m3/io/sam3_spi.h
index 7024365b..794b1812 100644
--- a/bertos/cpu/cortex-m3/io/sam3_spi.h
+++ b/bertos/cpu/cortex-m3/io/sam3_spi.h
@@ -78,6 +78,9 @@
* SPI base addresses.
*/
#define SPI0_BASE 0x40008000
+#if CPU_CM3_SAM3X
+ #define SPI1_BASE 0x4000C000
+#endif
/**
* SPI Control Register
diff --git a/bertos/cpu/cortex-m3/io/sam3_sysctl.h b/bertos/cpu/cortex-m3/io/sam3_sysctl.h
index f83cce21..6853d067 100644
--- a/bertos/cpu/cortex-m3/io/sam3_sysctl.h
+++ b/bertos/cpu/cortex-m3/io/sam3_sysctl.h
@@ -37,7 +37,11 @@
#define SAM3_SYSCTL_H
/** Supply controller base */
-#define SUPC_BASE 0x400E1410
+#if CPU_CM3_SAM3X
+ #define SUPC_BASE 0x400E1A10
+#else
+ #define SUPC_BASE 0x400E1410
+#endif
/**
* Supply controller offsets.
diff --git a/bertos/cpu/cortex-m3/io/sam3_uart.h b/bertos/cpu/cortex-m3/io/sam3_uart.h
index 9a4e12b5..97ad3ff2 100644
--- a/bertos/cpu/cortex-m3/io/sam3_uart.h
+++ b/bertos/cpu/cortex-m3/io/sam3_uart.h
@@ -40,9 +40,13 @@
* UART registers base addresses.
*/
/*\{*/
-#define UART0_BASE 0x400E0600
-#ifndef CPU_CM3_SAM3U
+#if CPU_CM3_SAM3N
+ #define UART0_BASE 0x400E0600
+#elif CPU_CM3_SAM3U
+ #define UART0_BASE 0x400E0600
#define UART1_BASE 0x400E0800
+#elif CPU_CM3_SAM3X
+ #define UART0_BASE 0x400E0800
#endif
/*\}*/
diff --git a/bertos/cpu/cortex-m3/io/sam3_usart.h b/bertos/cpu/cortex-m3/io/sam3_usart.h
index 405c0890..dd78c511 100644
--- a/bertos/cpu/cortex-m3/io/sam3_usart.h
+++ b/bertos/cpu/cortex-m3/io/sam3_usart.h
@@ -74,14 +74,19 @@
/**
* USART base addresses.
*/
-#if CPU_CM3_SAM3U
+#if CPU_CM3_SAM3N
+ #define USART0_BASE 0x40024000
+ #define USART1_BASE 0x40028000
+#elif CPU_CM3_SAM3U
#define USART0_BASE 0x40090000
#define USART1_BASE 0x40094000
#define USART2_BASE 0x40098000
#define USART3_BASE 0x4009C000
-#else
- #define USART0_BASE 0x40024000
- #define USART1_BASE 0x40028000
+#elif CPU_CM3_SAM3X
+ #define USART0_BASE 0x40098000
+ #define USART1_BASE 0x4009C000
+ #define USART2_BASE 0x400A0000
+ #define USART3_BASE 0x400A4000
#endif
/**
diff --git a/bertos/cpu/cortex-m3/io/sam3_wdt.h b/bertos/cpu/cortex-m3/io/sam3_wdt.h
index 8c8325ca..b57d06ee 100644
--- a/bertos/cpu/cortex-m3/io/sam3_wdt.h
+++ b/bertos/cpu/cortex-m3/io/sam3_wdt.h
@@ -73,7 +73,11 @@
#define SAM3_WDT_H
/** Watch Dog registers base address */
-#define WDT_BASE 0x400E1450
+#if CPU_CM3_SAM3N
+ #define WDT_BASE 0x400E1450
+#elif CPU_CM3_SAM3X
+ #define WDT_BASE 0x400E1A50
+#endif
/** Watch Dog Control Register */
/*\{*/