From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Thu, 22 Apr 2010 21:57:33 +0000 (+0000)
Subject: lm3s1968: set the correct GPIO registers when enabling the peripheral clock for UART1... 
X-Git-Tag: 2.5.0~412
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=c969705a2b1656920c1c2207ba39c75f3dca2538;p=bertos.git

lm3s1968: set the correct GPIO registers when enabling the peripheral clock for UART1 and UART2.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3496 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/ser_lm3s.c b/bertos/cpu/cortex-m3/drv/ser_lm3s.c
index 89ce1322..717ffa58 100644
--- a/bertos/cpu/cortex-m3/drv/ser_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/ser_lm3s.c
@@ -61,6 +61,8 @@ static struct CM3Serial UARTDesc[SER_CNT];
 /* GPIO descriptor for UART pins */
 struct gpio_uart_info
 {
+	/* Sysctl */
+	uint32_t sysctl;
 	/* GPIO base address register */
 	uint32_t base;
 	/* Pin(s) bitmask */
@@ -74,16 +76,19 @@ static const struct gpio_uart_info gpio_uart[SER_CNT] =
 	{
 		.base = GPIO_PORTA_BASE,
 		.pins = BV(1) | BV(0),
+		.sysctl = SYSCTL_RCGC2_GPIOA,
 	},
 	/* UART1 */
 	{
 		.base = GPIO_PORTD_BASE,
 		.pins = BV(3) | BV(2),
+		.sysctl = SYSCTL_RCGC2_GPIOD,
 	},
 	/* UART2 */
 	{
 		.base = GPIO_PORTG_BASE,
 		.pins = BV(1) | BV(0),
+		.sysctl = SYSCTL_RCGC2_GPIOG,
 	},
 };
 
@@ -153,7 +158,7 @@ void lm3s_uartInit(int port)
 
 	/* Enable the peripheral clock */
 	SYSCTL_RCGC1_R |= reg_clock;
-	SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
+	SYSCTL_RCGC2_R |= gpio_uart[port].sysctl;
 	lm3s_busyWait(512);
 
 	/* Configure GPIO pins to work as UART pins */