From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Thu, 13 May 2010 13:20:43 +0000 (+0000)
Subject: ARM7TDMI: optimize IRQ macros.
X-Git-Tag: 2.5.0~238
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=d024efae0a3d5ccdc95de2beb740413582b06baa;p=bertos.git

ARM7TDMI: optimize IRQ macros.

Instead of using register "r0" explicitly in IRQ_ENABLE(),
IRQ_DISABLE(), etc. consider to let the compiler decide the best
register to use.

Moreover, add "memory" to the clobber list so that all the IRQ functions
implicitly add a memory barrier. In this way we're sure memory operation
ordering is always preserved on either side of the IRQ operation.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3679 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/irq.h b/bertos/cpu/irq.h
index c3824556..60acce21 100644
--- a/bertos/cpu/irq.h
+++ b/bertos/cpu/irq.h
@@ -239,59 +239,55 @@
 
 	#else /* !__IAR_SYSTEMS_ICC__ */
 
-		#define IRQ_DISABLE \
-		do { \
-			asm volatile ( \
-				"mrs r0, cpsr\n\t" \
-				"orr r0, r0, #0xc0\n\t" \
-				"msr cpsr_c, r0" \
-				::: "r0" \
-			); \
+		#define IRQ_DISABLE					\
+		do {							\
+			cpu_flags_t sreg;				\
+			asm volatile (					\
+				"mrs %0, cpsr\n\t"			\
+				"orr %0, %0, #0xc0\n\t"			\
+				"msr cpsr_c, %0\n\t"			\
+				: "=r" (sreg) : : "memory", "cc");	\
 		} while (0)
 
-		#define IRQ_ENABLE \
-		do { \
-			asm volatile ( \
-				"mrs r0, cpsr\n\t" \
-				"bic r0, r0, #0xc0\n\t" \
-				"msr cpsr_c, r0" \
-				::: "r0" \
-			); \
+		#define IRQ_ENABLE					\
+		do {							\
+			cpu_flags_t sreg;				\
+			asm volatile (					\
+				"mrs %0, cpsr\n\t"			\
+				"bic %0, %0, #0xc0\n\t"			\
+				"msr cpsr_c, %0\n\t"			\
+				: "=r" (sreg) : : "memory", "cc");	\
 		} while (0)
 
-		#define IRQ_SAVE_DISABLE(x) \
-		do { \
-			asm volatile ( \
-				"mrs %0, cpsr\n\t" \
-				"orr r0, %0, #0xc0\n\t" \
-				"msr cpsr_c, r0" \
-				: "=r" (x) \
-				: /* no inputs */ \
-				: "r0" \
-			); \
+		#define IRQ_SAVE_DISABLE(x)				\
+		do {							\
+			cpu_flags_t sreg;				\
+			(void) (&sreg == &x);				\
+			asm volatile (					\
+				"mrs %0, cpsr\n\t"			\
+				"orr %1, %0, #0xc0\n\t"			\
+				"msr cpsr_c, %1\n\t"			\
+				: "=r" (x), "=r" (sreg)			\
+				: : "memory", "cc");			\
 		} while (0)
 
-		#define IRQ_RESTORE(x) \
-		do { \
-			asm volatile ( \
-				"msr cpsr_c, %0" \
-				: /* no outputs */ \
-				: "r" (x) \
-			); \
+		#define IRQ_RESTORE(x)					\
+		do {							\
+			asm volatile (					\
+				"msr cpsr_c, %0\n\t"			\
+				: : "r" (x) : "memory", "cc");		\
 		} while (0)
 
-		#define CPU_READ_FLAGS() \
-		({ \
-			cpu_flags_t sreg; \
-			asm volatile ( \
-				"mrs %0, cpsr\n\t" \
-				: "=r" (sreg) \
-				: /* no inputs */ \
-			); \
-			sreg; \
+		#define CPU_READ_FLAGS()				\
+		({							\
+			cpu_flags_t sreg;				\
+			asm volatile (					\
+				"mrs %0, cpsr\n\t"			\
+				: "=r" (sreg) : : "memory", "cc");	\
+			sreg;						\
 		})
 
-		#define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
+		#define IRQ_ENABLED() (!(CPU_READ_FLAGS() & 0x80))
 
 		#if CONFIG_KERN_PREEMPT
 			EXTERN_C void asm_irq_switch_context(void);