From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Mon, 28 Jun 2010 18:16:39 +0000 (+0000)
Subject: Reformat. Clean up. Use more clear variable names.
X-Git-Tag: 2.6.0~343
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=d6f90fa0d64d7e8a6ae6ececc3c2052938bf8f25;p=bertos.git

Reformat. Clean up. Use more clear variable names.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3964 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/ser_stm32.c b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 081a0579..a74b7fe0 100644
--- a/bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/ser_stm32.c
@@ -72,8 +72,8 @@ struct gpio_uart_info
 	uint32_t rx_pin;
 	uint32_t tx_pin;
 	/* Sysctl */
-	uint32_t sysctl;
-	uint32_t sysctl1;
+	uint32_t sysctl_gpio;
+	uint32_t sysctl_usart;
 
 };
 
@@ -85,24 +85,24 @@ static const struct gpio_uart_info gpio_uart[SER_CNT] =
 		.base = GPIOA_BASE,
 		.rx_pin = GPIO_USART1_RX_PIN,
 		.tx_pin = GPIO_USART1_TX_PIN,
-		.sysctl = RCC_APB2_GPIOA,
-		.sysctl1 = RCC_APB2_USART1,
+		.sysctl_gpio = RCC_APB2_GPIOA,
+		.sysctl_usart = RCC_APB2_USART1,
 	},
 	/* UART2 */
 	{
 		.base = GPIOA_BASE,
 		.rx_pin = GPIO_USART2_RX_PIN,
 		.tx_pin = GPIO_USART2_TX_PIN,
-		.sysctl = RCC_APB2_GPIOA,
-		.sysctl1 = RCC_APB1_USART2,
+		.sysctl_gpio = RCC_APB2_GPIOA,
+		.sysctl_usart = RCC_APB1_USART2,
 	},
 	/* UART3 */
 	{
 		.base = GPIOB_BASE,
 		.rx_pin = GPIO_USART3_RX_PIN,
 		.tx_pin = GPIO_USART3_TX_PIN,
-		.sysctl = RCC_APB2_GPIOB,
-		.sysctl1 = RCC_APB1_USART3,
+		.sysctl_gpio = RCC_APB2_GPIOB,
+		.sysctl_usart = RCC_APB1_USART3,
 	},
 };
 
@@ -149,16 +149,16 @@ void stm32_uartInit(int port)
 
 	/* Enable clocking on AFIO */
 	RCC->APB2ENR |= RCC_APB2_AFIO;
-	RCC->APB2ENR |=  gpio_uart[port].sysctl;
+	RCC->APB2ENR |= gpio_uart[port].sysctl_gpio;
 
 	/* Configure USART pins */
 	if (port == USART1_PORT)
 	{
-		RCC->APB2ENR |=  gpio_uart[port].sysctl1;
+		RCC->APB2ENR |=  gpio_uart[port].sysctl_usart;
 	}
 	else
 	{
-		RCC->APB1ENR |=  gpio_uart[port].sysctl1;
+		RCC->APB1ENR |=  gpio_uart[port].sysctl_usart;
 	}
 
 	stm32_gpioPinConfig((struct stm32_gpio *)gpio_uart[port].base,  gpio_uart[port].tx_pin,
@@ -168,9 +168,9 @@ void stm32_uartInit(int port)
 				GPIO_MODE_IN_FLOATING, GPIO_SPEED_50MHZ);
 
 	/* Clear control registry */
-	base->CR2 = 0; //CR2_CLEAR_MASK;
-	base->CR1 = 0; //CR1_CLEAR_MASK;
-	base->CR3 = 0; //CR3_CLEAR_MASK;
+	base->CR2 = 0;
+	base->CR1 = 0;
+	base->CR3 = 0;
 	base->SR = 0;
 
 	/* Set serial param: 115.200 bps, no parity */
diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h
index 24bd2479..09bb0748 100644
--- a/bertos/cpu/cortex-m3/io/stm32_adc.h
+++ b/bertos/cpu/cortex-m3/io/stm32_adc.h
@@ -272,7 +272,7 @@
 /* ADC registers Masks */
 #define CR1_ADC_CLEAR_MASK             ((uint32_t)0xFFF0FEFF)
 #define CR2_ADC_CLEAR_MASK             ((uint32_t)0xFFF1F7FD)
-#define SQR1_CLEAR_MASK            ((uint32_t)0xFF0FFFFF)
+#define SQR1_CLEAR_MASK                ((uint32_t)0xFF0FFFFF)