From: batt Date: Tue, 23 Oct 2007 14:58:18 +0000 (+0000) Subject: Move IRQ_ENTRY and IRQ_EXIT macros to cpu/irq.h. X-Git-Tag: 1.0.0~311 X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=d9f99c9f43f39c988c2df5bab952818105f5cb58;p=bertos.git Move IRQ_ENTRY and IRQ_EXIT macros to cpu/irq.h. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@931 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/cpu/arm/io/at91.h b/cpu/arm/io/at91.h index 840fb59a..0c2feb15 100644 --- a/cpu/arm/io/at91.h +++ b/cpu/arm/io/at91.h @@ -75,27 +75,6 @@ #include -/** - * Interrupt entry point. - * Needed because AT91 uses an Interrupt Controller with auto-vectoring. - */ -#define IRQ_ENTRY() \ - asm volatile("sub lr, lr,#4" "\n\t" /* Adjust LR */ \ - "stmfd sp!,{r0-r12,lr}" "\n\t" /* Save registers on IRQ stack. */ \ - "mrs r1, spsr" "\n\t" /* Save SPSR */ \ - "stmfd sp!,{r1}" "\n\t") /* */ - -/** - * Interrupt exit. - * Needed because AT91 uses an Interrupt Controller with auto-vectoring. - */ -#define IRQ_EXIT() \ - asm volatile("ldmfd sp!, {r1}" "\n\t" /* Restore SPSR */ \ - "msr spsr_c, r1" "\n\t" /* */ \ - "ldr r0, =0xFFFFF000" "\n\t" /* End of interrupt. */ \ - "str r0, [r0, #0x130]" "\n\t" /* */ \ - "ldmfd sp!, {r0-r12, pc}^" "\n\t") /* Restore registers and return. */ - #if CPU_ARM_AT91SAM7S256 #include "at91sam7s256.h" #else diff --git a/cpu/irq.h b/cpu/irq.h index 428ba2d7..31c2bc79 100644 --- a/cpu/irq.h +++ b/cpu/irq.h @@ -151,6 +151,28 @@ #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0) + /** + * Interrupt entry point. + * Needed because AT91 uses an Interrupt Controller with auto-vectoring. + */ + #define IRQ_ENTRY() \ + asm volatile("sub lr, lr,#4" "\n\t" /* Adjust LR */ \ + "stmfd sp!,{r0-r12,lr}" "\n\t" /* Save registers on IRQ stack. */ \ + "mrs r1, spsr" "\n\t" /* Save SPSR */ \ + "stmfd sp!,{r1}" "\n\t") /* */ + + /** + * Interrupt exit. + * Needed because AT91 uses an Interrupt Controller with auto-vectoring. + */ + #define IRQ_EXIT() \ + asm volatile("ldmfd sp!, {r1}" "\n\t" /* Restore SPSR */ \ + "msr spsr_c, r1" "\n\t" /* */ \ + "ldr r0, =0xFFFFF000" "\n\t" /* End of interrupt. */ \ + "str r0, [r0, #0x130]" "\n\t" /* */ \ + "ldmfd sp!, {r0-r12, pc}^" "\n\t") /* Restore registers and return. */ + + #endif /* !__IAR_SYSTEMS_ICC_ */ #elif CPU_PPC @@ -220,6 +242,15 @@ #error No CPU_... defined. #endif +#ifndef IRQ_ENTRY + #define IRQ_ENTRY() /* NOP */ +#endif + +#ifndef IRQ_EXIT + #define IRQ_EXIT() /* NOP */ +#endif + + /** * Execute \a CODE atomically with respect to interrupts. *