From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Thu, 21 Feb 2008 18:09:59 +0000 (+0000)
Subject: Fix paste bug.
X-Git-Tag: 1.0.0~106
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=da0ee63685fa7ddd25d99225178b396601773c79;p=bertos.git

Fix paste bug.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1146 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/cpu/arm/io/at91_tc.h b/cpu/arm/io/at91_tc.h
index 5a9772eb..080d5881 100644
--- a/cpu/arm/io/at91_tc.h
+++ b/cpu/arm/io/at91_tc.h
@@ -269,9 +269,9 @@
 #define TC2_IDR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) ///< Channel 2 interrupt disable register address.
 
 #define TC_IMR_OFF              0x0000002C      ///< Interrupt Mask Register offset.
-#define TC0_IMR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) ///< Channel 0 interrupt mask register address.
-#define TC1_IMR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) ///< Channel 1 interrupt mask register address.
-#define TC2_IMR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) ///< Channel 2 interrupt mask register address.
+#define TC0_IMR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) ///< Channel 0 interrupt mask register address.
+#define TC1_IMR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) ///< Channel 1 interrupt mask register address.
+#define TC2_IMR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) ///< Channel 2 interrupt mask register address.
 
 #define TC_COVFS                         0      ///< Counter overflow flag.
 #define TC_LOVRS                         1      ///< Load overrun flag.