From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Wed, 12 May 2010 12:15:31 +0000 (+0000)
Subject: STM32: initialize the clock for all the peripherals at boot.
X-Git-Tag: 2.5.0~257
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=dc9b8ecb40cb399616ef3044b7c1b29cf9cf76b4;p=bertos.git

STM32: initialize the clock for all the peripherals at boot.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3660 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index cd8e0f42..4b8cd898 100644
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -126,8 +126,23 @@ void clock_init(void)
 	rcc_pll_config();
 	while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
 
+	/* Configure USB clock (48MHz) */
+	*CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
+	/* Configure ADC clock: PCLK2 (9MHz) */
+	RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
+	RCC->CFGR |= RCC_PCLK2_DIV8;
+	/* Configure system clock dividers: PCLK2 (72MHz) */
+	RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
+	RCC->CFGR |= RCC_HCLK_DIV1 << 3;
+	/* Configure system clock dividers: PCLK1 (36MHz) */
+	RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
+	RCC->CFGR |= RCC_HCLK_DIV2 << 3;
+	/* Configure system clock dividers: HCLK */
+	RCC->CFGR &= CFGR_HPRE_RESET_MASK;
+	RCC->CFGR |= RCC_SYSCLK_DIV1;
+
 	/* Set 1 wait state for the flash memory */
-	*(reg32_t *)0x40022000 = 0x12;
+	*(reg32_t *)FLASH_BASE = 0x12;
 
 	/* Clock the system from the PLL */
 	rcc_set_clock_source(RCC_SYSCLK_PLLCLK);
diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.h b/bertos/cpu/cortex-m3/drv/clock_stm32.h
index c675a5f8..4150a44d 100644
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.h
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.h
@@ -171,6 +171,34 @@
 #define RCC_PLLMUL_14              (0x00300000)
 #define RCC_PLLMUL_15              (0x00340000)
 #define RCC_PLLMUL_16              (0x00380000)
+
+/* APB1/APB2 clock source */
+#define RCC_HCLK_DIV1              (0x00000000)
+#define RCC_HCLK_DIV2              (0x00000400)
+#define RCC_HCLK_DIV4              (0x00000500)
+#define RCC_HCLK_DIV8              (0x00000600)
+#define RCC_HCLK_DIV16             (0x00000700)
+
+/* USB clock source */
+#define RCC_USBCLK_PLLCLK_1DIV5    (0x00)
+#define RCC_USBCLK_PLLCLK_DIV1     (0x01)
+
+/* ADC clock source */
+#define RCC_PCLK2_DIV2             (0x00000000)
+#define RCC_PCLK2_DIV4             (0x00004000)
+#define RCC_PCLK2_DIV6             (0x00008000)
+#define RCC_PCLK2_DIV8             (0x0000C000)
+
+/* AHB clock source */
+#define RCC_SYSCLK_DIV1            (0x00000000)
+#define RCC_SYSCLK_DIV2            (0x00000080)
+#define RCC_SYSCLK_DIV4            (0x00000090)
+#define RCC_SYSCLK_DIV8            (0x000000A0)
+#define RCC_SYSCLK_DIV16           (0x000000B0)
+#define RCC_SYSCLK_DIV64           (0x000000C0)
+#define RCC_SYSCLK_DIV128          (0x000000D0)
+#define RCC_SYSCLK_DIV256          (0x000000E0)
+#define RCC_SYSCLK_DIV512          (0x000000F0)
 /*\}*/
 
 /**