From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Thu, 24 Jan 2008 14:50:39 +0000 (+0000)
Subject: Add support for at91sam7x cpu.
X-Git-Tag: 1.0.0~179
X-Git-Url: https://codewiz.org/gitweb?a=commitdiff_plain;h=e66586db26103723ef23c549b1dd778548d1796c;p=bertos.git

Add support for at91sam7x cpu.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1063 38d2e660-2303-0410-9eaa-f027e97ec537
---

diff --git a/cpu/arm/io/at91sam7.h b/cpu/arm/io/at91sam7.h
new file mode 100644
index 00000000..f91690e8
--- /dev/null
+++ b/cpu/arm/io/at91sam7.h
@@ -0,0 +1,242 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \version $Id$
+ *
+ * \author Francesco Sacchi <batt@develer.com>
+ * \author Daniele Basile <asterix@develer.com>
+ *
+ * AT91SAM7 register definitions.
+ * This file is based on NUT/OS implementation. See license below.
+ */
+
+/*
+ * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+#ifndef AT91SAM7_H
+#define AT91SAM7_H
+
+#include <cfg/compiler.h>
+
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+	#define FLASH_BASE      0x100000UL
+	#define RAM_BASE        0x200000UL
+
+	#define TC_BASE         0xFFFA0000      ///< Timer/counter base address.
+	#define UDP_BASE        0xFFFB0000      ///< USB device port base address.
+	#define TWI_BASE        0xFFFB8000      ///< Two-wire interface base address.
+	#define USART0_BASE     0xFFFC0000      ///< USART 0 base address.
+	#define USART1_BASE     0xFFFC4000      ///< USART 1 base address.
+	#define PWMC_BASE       0xFFFCC000      ///< PWM controller base address.
+	#define SSC_BASE        0xFFFD4000      ///< Serial synchronous controller base address.
+	#define ADC_BASE        0xFFFD8000      ///< ADC base address.
+
+	#define AIC_BASE        0xFFFFF000      ///< AIC base address.
+	#define DBGU_BASE       0xFFFFF200      ///< DBGU base address.
+	#define PIOA_BASE       0xFFFFF400      ///< PIO A base address.
+	#define PMC_BASE        0xFFFFFC00      ///< PMC base address.
+	#define RSTC_BASE       0xFFFFFD00      ///< Resect controller register base address.
+	#define RTT_BASE        0xFFFFFD20      ///< Realtime timer base address.
+	#define PIT_BASE        0xFFFFFD30      ///< Periodic interval timer base address.
+	#define WDT_BASE        0xFFFFFD40      ///< Watch Dog register base address.
+	#define VREG_BASE       0xFFFFFD60      ///< Voltage regulator mode controller base address.
+	#define MC_BASE         0xFFFFFF00      ///< Memory controller base.
+
+	#if CPU_ARM_AT91SAM7X256
+		#define CAN_BASE        0xFFFD0000      ///< PWM controller base address.
+		#define EMAC_BASE       0xFFFDC000      ///< Ethernet MAC address.
+		#define SPI0_BASE       0xFFFE0000      ///< SPI0 base address.
+		#define SPI1_BASE       0xFFFE4000      ///< SPI1 base address.
+		#define PIOB_BASE       0xFFFFF600      ///< PIO base address.
+	#endif
+
+	#if CPU_ARM_AT91SAM7S256
+		#define SPI_BASE        0xFFFE0000      ///< SPI0 base address.
+	#endif
+
+	#define PIO_HAS_MULTIDRIVER        1
+	#define PIO_HAS_PULLUP             1
+	#define PIO_HAS_PERIPHERALSELECT   1
+	#define PIO_HAS_OUTPUTWRITEENABLE  1
+
+	#define DBGU_HAS_PDC               1
+	#define SPI_HAS_PDC                1
+	#define SSC_HAS_PDC                1
+	#define USART_HAS_PDC              1
+
+#else
+	#error No base addrese register definition for selected ARM CPU
+
+#endif
+
+#include "at91_aic.h"
+#include "at91_pit.h"
+#include "at91_pmc.h"
+#include "at91_mc.h"
+#include "at91_wdt.h"
+#include "at91_rstc.h"
+#include "at91_pio.h"
+#include "at91_us.h"
+#include "at91_dbgu.h"
+//TODO: add other peripherals
+
+/**
+ * Peripheral Identifiers and Interrupts
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+	#define FIQ_ID      0       ///< Fast interrupt ID.
+	#define SYSC_ID     1       ///< System controller interrupt.
+	#define US0_ID      6       ///< USART 0 ID.
+	#define US1_ID      7       ///< USART 1 ID.
+	#define SSC_ID      8       ///< Synchronous serial controller ID.
+	#define TWI_ID      9       ///< Two-wire interface ID.
+	#define PWMC_ID     10      ///< PWM controller ID.
+	#define UDP_ID      11      ///< USB device port ID.
+	#define TC0_ID      12      ///< Timer 0 ID.
+	#define TC1_ID      13      ///< Timer 1 ID.
+	#define TC2_ID      14      ///< Timer 2 ID.
+
+	#define IRQ0_ID     30      ///< External interrupt 0 ID.
+	#define IRQ1_ID     31      ///< External interrupt 1 ID.
+
+	#if CPU_ARM_AT91SAM7X256
+		#define PIOA_ID     2       ///< Parallel A I/O controller ID.
+		#define PIOB_ID     3       ///< Parallel B I/O controller ID.
+		#define SPI0_ID     4       ///< Serial peripheral interface 0 ID.
+		#define SPI1_ID     5       ///< Serial peripheral interface 1 ID.
+		#define CAN_ID      15      ///< CAN controller ID.
+		#define EMAC_ID     16      ///< Ethernet MAC ID.
+		#define ADC_ID      17      ///< Analog to digital converter ID.
+		/* 18-29 Reserved */
+
+	#endif
+
+	#if CPU_ARM_AT91SAM7S256
+		#define PIOA_ID     2       ///< Parallel I/O controller ID.
+		/* ID 3 is reserved */
+		#define ADC_ID      4       ///< Analog to digital converter ID.
+		#define SPI_ID      5       ///< Serial peripheral interface ID.
+
+	#endif
+
+#else
+	#error No peripheral ID and interrupts definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * USART pins name
+ *\{
+ */
+#if CPU_ARM_AT91SAM7S256
+	#define RXD0        5
+	#define TXD0        6
+	#define RXD1       21
+	#define TXD1       22
+
+#elif CPU_ARM_AT91SAM7X256
+	#define RXD0       0 // PA0
+	#define TXD0       1 // PA1
+	#define RXD1       5 // PA5
+	#define TXD1       6 // PA6
+
+#else
+	#error No USART pins name definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * SPI pins name
+ *\{
+ */
+#if CPU_ARM_AT91SAM7S256
+	#define NPCS0      11  // Same as NSS pin.
+	#define MISO       12
+	#define MOSI       13
+	#define SPCK       14
+
+#elif CPU_ARM_AT91SAM7X256
+	#define SPI0_NPCS0  12 // Same as NSS pin. PA12
+	#define SPI0_NPCS1  13 // PA13
+	#define SPI0_NPCS2  14 // PA14
+	#define SPI0_NPCS3  15 // PA15
+	#define SPI0_MISO   16 // PA16
+	#define SPI0_MOSI   17 // PA17
+	#define SPI0_SPCK   18 // PA18
+
+	#define SPI1_NPCS0  21 // Same as NSS pin. PA21
+	#define SPI1_NPCS1  25 // PA25
+	#define SPI1_NPCS2  26 // PA26
+	#define SPI1_NPCS3  29 // PA29
+	#define SPI1_MISO   24 // PA24
+	#define SPI1_MOSI   23 // PA23
+	#define SPI1_SPCK   22 // PA22
+
+#else
+	#error No SPI pins name definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+#endif /* AT91SAM7_H */
diff --git a/cpu/arm/io/at91sam7s256.h b/cpu/arm/io/at91sam7s256.h
deleted file mode 100644
index 98fd66d5..00000000
--- a/cpu/arm/io/at91sam7s256.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction.  Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License.  This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
- *
- * -->
- *
- * \version $Id$
- *
- * \author Francesco Sacchi <batt@develer.com>
- *
- * AT91SAM7S256 register definitions.
- * This file is based on NUT/OS implementation. See license below.
- */
-
-/*
- * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
- * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * For additional information see http://www.ethernut.de/
- */
-
-#ifndef AT91SAM7S256_H
-#define AT91SAM7S256_H
-
-#include <cfg/compiler.h>
-
-#define FLASH_BASE      0x100000UL
-#define RAM_BASE        0x200000UL
-
-#define TC_BASE         0xFFFA0000      ///< Timer/counter base address.
-#define UDP_BASE        0xFFFB0000      ///< USB device port base address.
-#define TWI_BASE        0xFFFB8000      ///< Two-wire interface base address.
-#define USART0_BASE     0xFFFC0000      ///< USART 0 base address.
-#define USART1_BASE     0xFFFC4000      ///< USART 1 base address.
-#define PWMC_BASE       0xFFFCC000      ///< PWM controller base address.
-#define SSC_BASE        0xFFFD4000      ///< Serial synchronous controller base address.
-#define ADC_BASE        0xFFFD8000      ///< ADC base address.
-#define SPI_BASE        0xFFFE0000      ///< SPI0 base address.
-
-#define AIC_BASE        0xFFFFF000      ///< AIC base address.
-#define DBGU_BASE       0xFFFFF200      ///< DBGU base address.
-#define PIOA_BASE       0xFFFFF400      ///< PIO A base address.
-#define PMC_BASE        0xFFFFFC00      ///< PMC base address.
-#define RSTC_BASE       0xFFFFFD00      ///< Resect controller register base address.
-#define RTT_BASE        0xFFFFFD20      ///< Realtime timer base address.
-#define PIT_BASE        0xFFFFFD30      ///< Periodic interval timer base address.
-#define WDT_BASE        0xFFFFFD40      ///< Watch Dog register base address.
-#define VREG_BASE       0xFFFFFD60      ///< Voltage regulator mode controller base address.
-#define MC_BASE         0xFFFFFF00      ///< Memory controller base.
-
-#define PIO_HAS_MULTIDRIVER        1
-#define PIO_HAS_PULLUP             1
-#define PIO_HAS_PERIPHERALSELECT   1
-#define PIO_HAS_OUTPUTWRITEENABLE  1
-
-#define DBGU_HAS_PDC               1
-#define SPI_HAS_PDC                1
-#define SSC_HAS_PDC                1
-#define USART_HAS_PDC              1
-
-#include "at91_aic.h"
-#include "at91_pit.h"
-#include "at91_pmc.h"
-#include "at91_mc.h"
-#include "at91_wdt.h"
-#include "at91_rstc.h"
-#include "at91_pio.h"
-#include "at91_us.h"
-#include "at91_dbgu.h"
-//TODO: add other peripherals
-
-/**
- * Peripheral Identifiers and Interrupts
- *\{
- */
-#define FIQ_ID      0       ///< Fast interrupt ID.
-#define SYSC_ID     1       ///< System controller interrupt.
-#define PIOA_ID     2       ///< Parallel I/O controller ID.
-/* ID 3 is reserved */
-#define ADC_ID      4       ///< Analog to digital converter ID.
-#define SPI_ID      5       ///< Serial peripheral interface ID.
-#define US0_ID      6       ///< USART 0 ID.
-#define US1_ID      7       ///< USART 1 ID.
-#define SSC_ID      8       ///< Synchronous serial controller ID.
-#define TWI_ID      9       ///< Two-wire interface ID.
-#define PWMC_ID     10      ///< PWM controller ID.
-#define UDP_ID      11      ///< USB device port ID.
-#define TC0_ID      12      ///< Timer 0 ID.
-#define TC1_ID      13      ///< Timer 1 ID.
-#define TC2_ID      14      ///< Timer 2 ID.
-
-#define IRQ0_ID     30      ///< External interrupt 0 ID.
-#define IRQ1_ID     31      ///< External interrupt 1 ID.
-/*\}*/
-
-/**
- * USART pins name
- *\{
- */
-#define RXD0        5
-#define TXD0        6
-#define RXD1       21
-#define TXD1       22
-/*\}*/
-
-/**
- * SPI pins name
- *\{
- */
-#define NPCS0      11  // Same as NSS pin.
-#define MISO       12
-#define MOSI       13
-#define SPCK       14
-/*\}*/
-
-#endif /* AT91SAM7S256_H */
diff --git a/cpu/detect.h b/cpu/detect.h
index 18247273..af2ecd07 100644
--- a/cpu/detect.h
+++ b/cpu/detect.h
@@ -41,6 +41,7 @@
 	#define CPU_ARM                 1
 	#define CPU_ID                  arm
 
+	// AT91SAM7S core family
 	#if defined(__ARM_AT91SAM7S32__)
 		#define CPU_ARM_AT91         1
 		#define CPU_ARM_AT91SAM7S32  1
@@ -69,11 +70,29 @@
 		#define CPU_ARM_AT91SAM7S256 0
 	#endif
 
+	// AT91SAM7X core family
+	#if defined(__ARM_AT91SAM7X128__)
+		#define CPU_ARM_AT91         1
+		#define CPU_ARM_AT91SAM7X128 1
+	#else
+		#define CPU_ARM_AT91SAM7X128 0
+	#endif
+
+	#if defined(__ARM_AT91SAM7X256__)
+		#define CPU_ARM_AT91         1
+		#define CPU_ARM_AT91SAM7X256 1
+	#else
+		#define CPU_ARM_AT91SAM7X256 0
+	#endif
+
+
 	#if defined(CPU_ARM_AT91)
 		#if CPU_ARM_AT91SAM7S32 + CPU_ARM_AT91SAM7S64 \
-		+ CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 != 1
+		+ CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 \
+		+ CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 != 1
 			#error ARM CPU configuration error
 		#endif
+
 	/* #elif Add other ARM families here */
 	#else
 		#define CPU_ATM_AT91         0
@@ -94,6 +113,8 @@
 	#define CPU_ARM_AT91SAM7S64     0
 	#define CPU_ARM_AT91SAM7S128    0
 	#define CPU_ARM_AT91SAM7S256    0
+	#define CPU_ARM_AT91SAM7X128    0
+	#define CPU_ARM_AT91SAM7X256    0
 #endif
 
 #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \