From 2d7a00fd39d1926c60ecfe615e100714797a5a79 Mon Sep 17 00:00:00 2001 From: asterix Date: Tue, 27 Sep 2011 10:20:19 +0000 Subject: [PATCH] Add internal flash driver for sam3x. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@5099 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/flash_cm3.h | 2 + bertos/cpu/cortex-m3/drv/flash_sam3.c | 247 ++++++++++++++++++++++++++ bertos/cpu/cortex-m3/drv/flash_sam3.h | 43 +++++ 3 files changed, 292 insertions(+) create mode 100644 bertos/cpu/cortex-m3/drv/flash_sam3.c create mode 100644 bertos/cpu/cortex-m3/drv/flash_sam3.h diff --git a/bertos/cpu/cortex-m3/drv/flash_cm3.h b/bertos/cpu/cortex-m3/drv/flash_cm3.h index 6b4bf11b..c6e2a831 100644 --- a/bertos/cpu/cortex-m3/drv/flash_cm3.h +++ b/bertos/cpu/cortex-m3/drv/flash_cm3.h @@ -41,6 +41,8 @@ #include "flash_lm3s.h" #elif CPU_CM3_STM32 #include "flash_stm32.h" +#elif CPU_CM3_SAM3 + #include "flash_sam3.h" /*#elif Add other Cortex-M3 CPUs here */ #else #error Unknown CPU diff --git a/bertos/cpu/cortex-m3/drv/flash_sam3.c b/bertos/cpu/cortex-m3/drv/flash_sam3.c new file mode 100644 index 00000000..fdafc2ae --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/flash_sam3.c @@ -0,0 +1,247 @@ +/** + * \file + * + * + * \author Daniele Basile + * + * \brief SAM3 Internal flash read/write driver. + * + * + */ + +#include "flash_sam3.h" + +#include "cfg/cfg_emb_flash.h" +#include + +// Define log settings for cfg/log.h +#define LOG_LEVEL CONFIG_FLASH_EMB_LOG_LEVEL +#define LOG_FORMAT CONFIG_FLASH_EMB_LOG_FORMAT +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + + +#define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size +#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes +#define FLASH_BANKS_NUM 2 ///< Number of flash banks +#define FLASH_BASE 0x0 + +struct FlashHardware +{ + uint8_t status; +}; + + +/** + * Really send the flash write command. + * + * \note This function has to be placed in RAM because + * executing code from flash while a writing process + * is in progress is forbidden. + */ +RAM_FUNC NOINLINE static void write_page(uint32_t page) +{ + // Send the 'write page' command + EEFC0_FCR = EEFC_FCR_FKEY | EFC_FCR_FCMD_EWP | EEFC_FCR_FARG(page); + + // Wait for the end of command + while(!(EEFC0_FSR & BV(EEFC_FSR_FRDY))) + { + //NOP; + } +} + + +/** + * Send write command. + * + * After WR command cpu write bufferd page into flash memory. + * + */ +INLINE void flash_sendWRcmd(uint32_t page) +{ + cpu_flags_t flags; + + LOG_INFO("Writing page %ld...\n", page); + + IRQ_SAVE_DISABLE(flags); + write_page(page); + + IRQ_RESTORE(flags); + LOG_INFO("Done\n"); +} + +/** + * Return true if no error are occurred after flash memory + * read or write operation, otherwise return error code. + */ +static bool flash_getStatus(struct KBlock *blk) +{ + Flash *fls = FLASH_CAST(blk); + /* + * This bit is set to one if an invalid command and/or a bad keywords was/were + * written in the Flash Command Register. + */ + if(EEFC0_FSR & BV(EEFC_FSR_FCMDE)) + { + fls->hw->status |= FLASH_WR_ERR; + LOG_ERR("flash not erased..\n"); + return false; + } + + /* + * This bit is set to one if we programming of at least one locked lock + * region. + */ + if(EEFC0_FSR & BV(EEFC_FSR_FLOCKE)) + { + fls->hw->status |= FLASH_WR_PROTECT; + LOG_ERR("wr protect..\n"); + return false; + } + + return true; +} + +static size_t sam3_flash_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size) +{ + memcpy(buf, (void *)(idx * blk->blk_size + FLASH_BASE + offset), size); + return size; +} + +static size_t sam3_flash_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size) +{ + ASSERT(offset == 0); + ASSERT(size == blk->blk_size); + + uint32_t *addr = (uint32_t *)(idx * blk->blk_size + FLASH_BASE); + const uint8_t *buf = (const uint8_t *)_buf; + + while (size) + { + uint32_t data = (*(buf + 3) << 24) | + (*(buf + 2) << 16) | + (*(buf + 1) << 8) | + *buf; + *addr = data; + + size -= 4; + buf += 4; + addr++; + } + + flash_sendWRcmd(idx); + + if (!flash_getStatus(blk)) + return 0; + + return blk->blk_size; +} + + +static int sam3_flash_error(struct KBlock *blk) +{ + Flash *fls = FLASH_CAST(blk); + return fls->hw->status; +} + +static void sam3_flash_clearerror(struct KBlock *blk) +{ + Flash *fls = FLASH_CAST(blk); + fls->hw->status = 0; +} + +static const KBlockVTable flash_sam3_buffered_vt = +{ + .readDirect = sam3_flash_readDirect, + .writeDirect = sam3_flash_writeDirect, + + .readBuf = kblock_swReadBuf, + .writeBuf = kblock_swWriteBuf, + .load = kblock_swLoad, + .store = kblock_swStore, + + .error = sam3_flash_error, + .clearerr = sam3_flash_clearerror, +}; + +static const KBlockVTable flash_sam3_unbuffered_vt = +{ + .readDirect = sam3_flash_readDirect, + .writeDirect = sam3_flash_writeDirect, + + .error = sam3_flash_error, + .clearerr = sam3_flash_clearerror, +}; + +static struct FlashHardware flash_sam3_hw; +static uint8_t flash_buf[FLASH_PAGE_SIZE_BYTES]; + +static void common_init(Flash *fls) +{ + memset(fls, 0, sizeof(*fls)); + DB(fls->blk.priv.type = KBT_FLASH); + + fls->hw = &flash_sam3_hw; + + fls->blk.blk_size = FLASH_PAGE_SIZE_BYTES; + fls->blk.blk_cnt = FLASH_MEM_SIZE / FLASH_PAGE_SIZE_BYTES; +} + +void flash_hw_init(Flash *fls, UNUSED_ARG(int, flags)) +{ + common_init(fls); + fls->blk.priv.vt = &flash_sam3_buffered_vt; + fls->blk.priv.flags |= KB_BUFFERED | KB_PARTIAL_WRITE; + fls->blk.priv.buf = flash_buf; + + /* Load the first block in the cache */ + memcpy(fls->blk.priv.buf, (void *)(FLASH_BASE), fls->blk.blk_size); +} + +void flash_hw_initUnbuffered(Flash *fls, UNUSED_ARG(int, flags)) +{ + common_init(fls); + fls->blk.priv.vt = &flash_sam3_unbuffered_vt; +} + diff --git a/bertos/cpu/cortex-m3/drv/flash_sam3.h b/bertos/cpu/cortex-m3/drv/flash_sam3.h new file mode 100644 index 00000000..36ed68d8 --- /dev/null +++ b/bertos/cpu/cortex-m3/drv/flash_sam3.h @@ -0,0 +1,43 @@ +/** + * \file + * + * + * \author Daniele Basile + * + * \brief SAM3 Internal flash read/write driver. + * + * + */ + +#ifndef FLASH_SAM3_H +#define FLASH_SAM3_H + +#endif /* FLASH_SAM3_H */ -- 2.25.1