From 0a4053ecfc25acc4b20c527ec8019e57498eb2e7 Mon Sep 17 00:00:00 2001 From: arighi Date: Fri, 9 Apr 2010 16:29:52 +0000 Subject: [PATCH] lm3s1968: rename the function __delay() to lm3s_busyWait(). git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3412 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/clock_lm3s.c | 8 ++++---- bertos/cpu/cortex-m3/drv/clock_lm3s.h | 2 +- bertos/cpu/cortex-m3/drv/kdebug_lm3s.c | 5 +++-- examples/lm3s1968/hw/hw_lcd.h | 2 +- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c index 1bc63f7a..76e901bd 100644 --- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c @@ -51,7 +51,7 @@ /* * Very small delay: each loop takes 3 cycles. */ -void NAKED __delay(unsigned long iterations) +void NAKED lm3s_busyWait(unsigned long iterations) { register uint32_t __n asm("r0") = iterations; @@ -113,7 +113,7 @@ void clock_set_rate(void) HWREG(SYSCTL_RCC) = rcc; HWREG(SYSCTL_RCC) = rcc2; - __delay(16); + lm3s_busyWait(16); /* * Step #2: select the crystal value (XTAL) and oscillator source @@ -139,7 +139,7 @@ void clock_set_rate(void) HWREG(SYSCTL_RCC) = rcc; HWREG(SYSCTL_RCC) = rcc2; - __delay(16); + lm3s_busyWait(16); /* * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and @@ -171,5 +171,5 @@ void clock_set_rate(void) HWREG(SYSCTL_RCC) = rcc; - __delay(16); + lm3s_busyWait(16); } diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.h b/bertos/cpu/cortex-m3/drv/clock_lm3s.h index 03940184..564afb17 100644 --- a/bertos/cpu/cortex-m3/drv/clock_lm3s.h +++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.h @@ -41,7 +41,7 @@ /* Crystal frequency attached to the main oscillator. */ #define XTAL_FREQ SYSCTL_RCC_XTAL_8MHZ -extern void __delay(unsigned long iterations); +extern void lm3s_busyWait(unsigned long iterations); unsigned long clock_get_rate(void); void clock_set_rate(void); diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c index e96c371f..d7be790a 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c @@ -37,7 +37,7 @@ #include #include /* for BV() */ -#include /* __delay() */ +#include /* lm3s_busyWait() */ #include #include #include "kdebug_lm3s.h" @@ -125,7 +125,8 @@ INLINE void kdbg_hw_init(void) /* Enable the peripheral clock */ SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0; SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA; - __delay(512); + lm3s_busyWait(512); + /* Set GPIO A0 and A1 as UART pins */ lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(0) | BV(1), GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); diff --git a/examples/lm3s1968/hw/hw_lcd.h b/examples/lm3s1968/hw/hw_lcd.h index c59dcb77..dd2d88d7 100644 --- a/examples/lm3s1968/hw/hw_lcd.h +++ b/examples/lm3s1968/hw/hw_lcd.h @@ -97,7 +97,7 @@ INLINE void lcd_bus_init(void) SYSCTL_RCGC1_R |= SYSCTL_RCGC1_SSI0; SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA; SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOH; - __delay(512); + lm3s_busyWait(512); /* Configure the SSI0CLK and SSIOTX pins for SSI operation. */ lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(2) | BV(3) | BV(5), -- 2.25.1