From 02dcaca92dc3681f413a81617db6d985d4b0a99b Mon Sep 17 00:00:00 2001
From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Wed, 12 May 2010 10:50:56 +0000
Subject: [PATCH] LM3S: remove kdebug dependency from serial driver.

This allows to create projects that use the kdebug module without
necessarily enabling the serial driver.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3658 38d2e660-2303-0410-9eaa-f027e97ec537
---
 bertos/cpu/cortex-m3/drv/kdebug_lm3s.c | 51 ++++++++++++++++++++++++--
 bertos/cpu/cortex-m3/drv/ser_lm3s.c    |  6 ---
 bertos/cpu/cortex-m3/drv/ser_lm3s.h    |  6 +++
 3 files changed, 54 insertions(+), 9 deletions(-)

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index c76ab8ec..64afa5ef 100644
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -39,7 +39,6 @@
 #include <cfg/macros.h> /* for BV() */
 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
 #include <drv/gpio_lm3s.h>
-#include <io/lm3s.h>
 #include <drv/ser_lm3s.h>
 #include "kdebug_lm3s.h"
 
@@ -47,10 +46,19 @@
 
 #if CONFIG_KDEBUG_PORT == 0
 	#define UART_BASE UART0_BASE
+	#define UART_GPIO_BASE GPIO_PORTA_BASE
+	#define UART_PINS (BV(1) | BV(0))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOA
 #elif CONFIG_KDEBUG_PORT == 1
 	#define UART_BASE UART1_BASE
+	#define UART_GPIO_BASE GPIO_PORTD_BASE
+	#define UART_PINS (BV(3) | BV(2))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOD
 #elif CONFIG_KDEBUG_PORT == 2
 	#define UART_BASE UART2_BASE
+	#define UART_GPIO_BASE GPIO_PORTG_BASE
+	#define UART_PINS (BV(1) | BV(0))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOG
 #else
 	#error "UART port not supported in this board"
 #endif
@@ -72,8 +80,45 @@ typedef uint32_t kdbg_irqsave_t;
 #error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
 #endif
 
+INLINE void uart_hw_config(void)
+{
+	unsigned long div, baud = CONFIG_KDEBUG_BAUDRATE;
+	bool hi_speed;
+
+	if (baud * 16 > CPU_FREQ)
+	{
+		hi_speed = true;
+		baud /= 2;
+	}
+	div = (CPU_FREQ * 8 / baud + 1) / 2;
+
+	lm3s_uartDisable(UART_BASE);
+	if (hi_speed)
+		HWREG(UART_BASE + UART_O_CTL) |= UART_CTL_HSE;
+	else
+		HWREG(UART_BASE + UART_O_CTL) &= ~UART_CTL_HSE;
+	/* Set the baud rate */
+	HWREG(UART_BASE + UART_O_IBRD) = div / 64;
+	HWREG(UART_BASE + UART_O_FBRD) = div % 64;
+	/* Set word lenght and parity */
+	HWREG(UART_BASE + UART_O_LCRH) = UART_LCRH_WLEN_8;
+	lm3s_uartClear(UART_BASE);
+	lm3s_uartEnable(UART_BASE);
+}
+
 INLINE void kdbg_hw_init(void)
 {
-	/* Initialize UART0 */
-	lm3s_uartInit(CONFIG_KDEBUG_PORT);
+	uint32_t reg_clock = 1 << CONFIG_KDEBUG_PORT;
+
+	/* Enable the peripheral clock */
+	SYSCTL_RCGC1_R |= reg_clock;
+	SYSCTL_RCGC2_R |= UART_REG_SYSCTL;
+	lm3s_busyWait(512);
+
+	/* Configure GPIO pins to work as UART pins */
+	lm3s_gpioPinConfig(UART_GPIO_BASE, UART_PINS,
+			GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+
+	/* Low-level UART configuration */
+	uart_hw_config();
 }
diff --git a/bertos/cpu/cortex-m3/drv/ser_lm3s.c b/bertos/cpu/cortex-m3/drv/ser_lm3s.c
index b326a058..8de8ce66 100644
--- a/bertos/cpu/cortex-m3/drv/ser_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/ser_lm3s.c
@@ -91,12 +91,6 @@ static const struct gpio_uart_info gpio_uart[SER_CNT] =
 	},
 };
 
-/* Clear the flags register */
-INLINE void lm3s_uartClear(uint32_t base)
-{
-	HWREG(base + UART_O_FR) = 0;
-}
-
 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
 {
 	unsigned long div;
diff --git a/bertos/cpu/cortex-m3/drv/ser_lm3s.h b/bertos/cpu/cortex-m3/drv/ser_lm3s.h
index 9485b1f8..e58738a8 100644
--- a/bertos/cpu/cortex-m3/drv/ser_lm3s.h
+++ b/bertos/cpu/cortex-m3/drv/ser_lm3s.h
@@ -91,6 +91,12 @@ INLINE void lm3s_uartEnable(uint32_t base)
 	lm3s_busyWait(512);
 }
 
+/* Clear the flags register */
+INLINE void lm3s_uartClear(uint32_t base)
+{
+	HWREG(base + UART_O_FR) = 0;
+}
+
 INLINE bool lm3s_uartTxDone(uint32_t base)
 {
 	return HWREG(base + UART_O_FR) & UART_FR_TXFE ? true : false;
-- 
2.25.1