From 0388fff030ba7086977f6641fa1b3469b772a57b Mon Sep 17 00:00:00 2001 From: batt Date: Mon, 15 Oct 2007 16:02:38 +0000 Subject: [PATCH] Add reset controller, watchdog and memory controller I/O register definitions. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@881 38d2e660-2303-0410-9eaa-f027e97ec537 --- cpu/arm/io/at91_mc.h | 153 +++++++++++++++++++++++++++++++++++++++++ cpu/arm/io/at91_pmc.h | 34 ++++----- cpu/arm/io/at91_rstc.h | 112 ++++++++++++++++++++++++++++++ cpu/arm/io/at91_wdt.h | 111 ++++++++++++++++++++++++++++++ cpu/arm/io/at91sam7s.h | 3 + 5 files changed, 396 insertions(+), 17 deletions(-) create mode 100644 cpu/arm/io/at91_mc.h create mode 100644 cpu/arm/io/at91_rstc.h create mode 100644 cpu/arm/io/at91_wdt.h diff --git a/cpu/arm/io/at91_mc.h b/cpu/arm/io/at91_mc.h new file mode 100644 index 00000000..c613c8bf --- /dev/null +++ b/cpu/arm/io/at91_mc.h @@ -0,0 +1,153 @@ +/** + * \file + * + * + * \version $Id$ + * + * \author Francesco Sacchi + * + * AT91 Memory controller. + * This file is based on NUT/OS implementation. See license below. + */ + +/* + * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE + * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * For additional information see http://www.ethernut.de/ + */ + +#ifndef AT91_MC_H +#define AT91_MC_H + +#define MC_RCR_OFF 0x00000000 ///< MC remap control register offset. +#define MC_RCR (*((volatile uint32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address. +#define MC_RCB 0 ///< Remap command. + +#define MC_ASR_OFF 0x00000004 ///< MC abort status register offset. +#define MC_ASR (*((volatile uint32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address. +#define MC_UNDADD 0 ///< Undefined Addess Abort status. +#define MC_MISADD 1 ///< Misaligned Addess Abort status. +#define MC_ABTSZ_MASK 0x00000300 ///< Abort size status mask. +#define MC_ABTSZ_BYTE 0x00000000 ///< Byte size abort. +#define MC_ABTSZ_HWORD 0x00000100 ///< Half-word size abort. +#define MC_ABTSZ_WORD 0x00000200 ///< Word size abort. +#define MC_ABTTYP_MASK 0x00000C00 ///< Abort type status mask. +#define MC_ABTTYP_DATAR 0x00000000 ///< Data read abort. +#define MC_ABTTYP_DATAW 0x00000400 ///< Data write abort. +#define MC_ABTTYP_FETCH 0x00000800 ///< Code fetch abort. +#define MC_MST_PDC 0x00020000 ///< PDC abort source. +#define MC_MST_ARM 0x00040000 ///< ARM abort source. +#define MC_SVMST_PDC 0x02000000 ///< Saved PDC abort source. +#define MC_SVMST_ARM 0x04000000 ///< Saved ARM abort source. + +#define MC_AASR_OFF 0x00000008 ///< MC abort address status register offset. +#define MC_AASR (*((volatile uint32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address. + +#define MC_FMR_OFF 0x00000060 ///< MC flash mode register offset. +#define MC_FMR (*((volatile uint32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address. +#define MC_FRDY 0 ///< Flash ready. +#define MC_LOCKE 2 ///< Lock error. +#define MC_PROGE 3 ///< Programming error. +#define MC_NEBP 7 ///< No erase before programming. +#define MC_FWS_MASK 0x00000300 ///< Flash wait state mask. +#define MC_FWS_1R2W 0x00000000 ///< 1 cycle for read, 2 for write operations. +#define MC_FWS_2R3W 0x00000100 ///< 2 cycles for read, 3 for write operations. +#define MC_FWS_3R4W 0x00000200 ///< 3 cycles for read, 4 for write operations. +#define MC_FWS_4R4W 0x00000300 ///< 4 cycles for read and write operations. +#define MC_FMCN_MASK 0x00FF0000 ///< Flash microsecond cycle number mask. + +#define MC_FCR_OFF 0x00000064 ///< MC flash command register offset. +#define MC_FCR (*((volatile uint32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address. +#define MC_FCMD_MASK 0x0000000F ///< Flash command mask. +#define MC_FCMD_NOP 0x00000000 ///< No command. +#define MC_FCMD_WP 0x00000001 ///< Write page. +#define MC_FCMD_SLB 0x00000002 ///< Set lock bit. +#define MC_FCMD_WPL 0x00000003 ///< Write page and lock. +#define MC_FCMD_CLB 0x00000004 ///< Clear lock bit. +#define MC_FCMD_EA 0x00000008 ///< Erase all. +#define MC_FCMD_SGPB 0x0000000B ///< Set general purpose NVM bit. +#define MC_FCMD_CGPB 0x0000000D ///< Clear general purpose NVM bit. +#define MC_FCMD_SSB 0x0000000F ///< Set security bit. +#define MC_PAGEN_MASK 0x0003FF00 ///< Page number mask. +#define MC_KEY 0x5A000000 ///< Writing protect key. + +#define MC_FSR_OFF 0x00000068 ///< MC flash status register offset. +#define MC_FSR (*((volatile uint32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address. +#define MC_SECURITY 4 ///< Security bit status. + +#define MC_GPNVM0 8 ///< General purpose NVM bit 0. +#define MC_GPNVM1 9 ///< General purpose NVM bit 1. +#define MC_GPNVM2 10 ///< General purpose NVM bit 2. + +#define MC_LOCKS0 16 ///< Lock region 0 lock status. +#define MC_LOCKS1 17 ///< Lock region 1 lock status. +#define MC_LOCKS2 18 ///< Lock region 2 lock status. +#define MC_LOCKS3 19 ///< Lock region 3 lock status. +#define MC_LOCKS4 20 ///< Lock region 4 lock status. +#define MC_LOCKS5 21 ///< Lock region 5 lock status. +#define MC_LOCKS6 22 ///< Lock region 6 lock status. +#define MC_LOCKS7 23 ///< Lock region 7 lock status. +#define MC_LOCKS8 24 ///< Lock region 8 lock status. +#define MC_LOCKS9 25 ///< Lock region 9 lock status. +#define MC_LOCKS10 26 ///< Lock region 10 lock status. +#define MC_LOCKS11 27 ///< Lock region 11 lock status. +#define MC_LOCKS12 28 ///< Lock region 12 lock status. +#define MC_LOCKS13 29 ///< Lock region 13 lock status. +#define MC_LOCKS14 30 ///< Lock region 14 lock status. +#define MC_LOCKS15 31 ///< Lock region 15 lock status. + +#endif /* AT91_MC_H */ diff --git a/cpu/arm/io/at91_pmc.h b/cpu/arm/io/at91_pmc.h index e2f5b864..35ecd766 100644 --- a/cpu/arm/io/at91_pmc.h +++ b/cpu/arm/io/at91_pmc.h @@ -76,11 +76,11 @@ /** System Clock Enable, Disable and Status Register */ /*\{*/ #define PMC_SCER_OFF 0x00000000 ///< System clock enable register offset. -#define PMC_SCER (PMC_BASE + PMC_SCER_OFF) ///< System clock enable register address. +#define PMC_SCER (*((volatile uint32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System clock enable register address. #define PMC_SCDR_OFF 0x00000004 ///< System clock disable register offset. -#define PMC_SCDR (PMC_BASE + PMC_SCDR_OFF) ///< System clock disable register address. +#define PMC_SCDR (*((volatile uint32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System clock disable register address. #define PMC_SCSR_OFF 0x00000008 ///< System clock status register offset. -#define PMC_SCSR (PMC_BASE + PMC_SCSR_OFF) ///< System clock status register address. +#define PMC_SCSR (*((volatile uint32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System clock status register address. #define PMC_PCK 0 ///< Processor clock. #define PMC_UDP 7 ///< USB device port clock. @@ -92,17 +92,17 @@ /** Peripheral Clock Enable, Disable and Status Register */ /*\{*/ #define PMC_PCER_OFF 0x00000010 ///< Peripheral clock enable register offset. -#define PMC_PCER (PMC_BASE + PMC_PCER_OFF) ///< Peripheral clock enable register address. +#define PMC_PCER (*((volatile uint32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral clock enable register address. #define PMC_PCDR_OFF 0x00000014 ///< Peripheral clock disable register offset. -#define PMC_PCDR (PMC_BASE + PMC_PCDR_OFF) ///< Peripheral clock disable register address. +#define PMC_PCDR (*((volatile uint32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral clock disable register address. #define PMC_PCSR_OFF 0x00000018 ///< Peripheral clock status register offset. -#define PMC_PCSR (PMC_BASE + PMC_PCSR_OFF) ///< Peripheral clock status register address. +#define PMC_PCSR (*((volatile uint32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral clock status register address. /*\}*/ /** Clock Generator Main Oscillator Register */ /*\{*/ #define CKGR_MOR_OFF 0x00000020 ///< Main oscillator register offset. -#define CKGR_MOR (PMC_BASE + CKGR_MOR_OFF) ///< Main oscillator register address. +#define CKGR_MOR (*((volatile uint32_t *)(PMC_BASE + CKGR_MOR_OFF))) ///< Main oscillator register address. #define CKGR_MOSCEN 0 ///< Main oscillator enable. #define CKGR_OSCBYPASS 1 ///< Main oscillator bypass. @@ -113,7 +113,7 @@ /** Clock Generator Main Clock Frequency Register */ /*\{*/ #define CKGR_MCFR_OFF 0x00000024 ///< Main clock frequency register offset. -#define CKGR_MCFR (PMC_BASE + CKGR_MCFR_OFF) ///< Main clock frequency register address. +#define CKGR_MCFR (*((volatile uint32_t *)(PMC_BASE + CKGR_MCFR_OFF))) ///< Main clock frequency register address. #define CKGR_MAINF_MASK 0x0000FFFF ///< Main clock frequency mask mask. #define CKGR_MAINRDY 16 ///< Main clock ready. @@ -122,7 +122,7 @@ /** PLL Registers */ /*\{*/ #define CKGR_PLLR_OFF 0x0000002C ///< Clock generator PLL register offset. -#define CKGR_PLLR (PMC_BASE + CKGR_PLLR_OFF) ///< Clock generator PLL register address. +#define CKGR_PLLR (*((volatile uint32_t *)(PMC_BASE + CKGR_PLLR_OFF))) ///< Clock generator PLL register address. #define CKGR_DIV_MASK 0x000000FF ///< Divider. #define CKGR_DIV_SHIFT 0 ///< Least significant bit of the divider. @@ -148,14 +148,14 @@ /** Master Clock Register */ /*\{*/ #define PMC_MCKR_OFF 0x00000030 ///< Master clock register offset. -#define PMC_MCKR (PMC_BASE + PMC_MCKR_OFF) ///< Master clock register address. +#define PMC_MCKR (*((volatile uint32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master clock register address. #define PMC_PCKR0_OFF 0x00000040 ///< Programmable clock 0 register offset. -#define PMC_PCKR0 (PMC_BASE + PMC_PCKR0_OFF) ///< Programmable clock 0 register address. +#define PMC_PCKR0 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR0_OFF))) ///< Programmable clock 0 register address. #define PMC_PCKR1_OFF 0x00000044 ///< Programmable clock 1 register offset. -#define PMC_PCKR1 (PMC_BASE + PMC_PCKR1_OFF) ///< Programmable clock 1 register address. +#define PMC_PCKR1 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR1_OFF))) ///< Programmable clock 1 register address. #define PMC_PCKR2_OFF 0x00000048 ///< Programmable clock 2 register offset. -#define PMC_PCKR2 (PMC_BASE + PMC_PCKR2_OFF) ///< Programmable clock 2 register address. +#define PMC_PCKR2 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR2_OFF))) ///< Programmable clock 2 register address. #define PMC_CSS_MASK 0x00000003 ///< Clock selection mask. #define PMC_CSS_SLOW_CLK 0x00000000 ///< Slow clock selected. @@ -176,13 +176,13 @@ /** Power Management Status and Interrupt Registers */ /*\{*/ #define PMC_IER_OFF 0x00000060 ///< Interrupt enable register offset. -#define PMC_IER (PMC_BASE + PMC_IER_OFF) ///< Interrupt enable register address. +#define PMC_IER (*((volatile uint32_t *)(PMC_BASE + PMC_IER_OFF))) ///< Interrupt enable register address. #define PMC_IDR_OFF 0x00000064 ///< Interrupt disable register offset. -#define PMC_IDR (PMC_BASE + PMC_IDR_OFF) ///< Interrupt disable register address. +#define PMC_IDR (*((volatile uint32_t *)(PMC_BASE + PMC_IDR_OFF))) ///< Interrupt disable register address. #define PMC_SR_OFF 0x00000068 ///< Status register offset. -#define PMC_SR (PMC_BASE + PMC_SR_OFF) ///< Status register address. +#define PMC_SR (*((volatile uint32_t *)(PMC_BASE + PMC_SR_OFF))) ///< Status register address. #define PMC_IMR_OFF 0x0000006C ///< Interrupt mask register offset. -#define PMC_IMR (PMC_BASE + PMC_IMR_OFF) ///< Interrupt mask register address. +#define PMC_IMR (*((volatile uint32_t *)(PMC_BASE + PMC_IMR_OFF))) ///< Interrupt mask register address. #define PMC_MOSCS 0 ///< Main oscillator. #define PMC_LOCK 2 ///< PLL lock. diff --git a/cpu/arm/io/at91_rstc.h b/cpu/arm/io/at91_rstc.h new file mode 100644 index 00000000..7e4c1a7a --- /dev/null +++ b/cpu/arm/io/at91_rstc.h @@ -0,0 +1,112 @@ +/** + * \file + * + * + * \version $Id$ + * + * \author Francesco Sacchi + * + * AT91 reset controller. + * This file is based on NUT/OS implementation. See license below. + */ + +/* + * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE + * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * For additional information see http://www.ethernut.de/ + */ + +#ifndef AT91_RTSC_H +#define AT91_RTSC_H + +/** Reset Controller Control Register */ +/*\{*/ +#define RSTC_CR (*((volatile uint32_t *)(RSTC_BASE + 0x00))) ///< Reset controller control register address. +#define RSTC_PROCRST 0 ///< Processor reset. +#define RSTC_PERRST 2 ///< Peripheral reset. +#define RSTC_EXTRST 3 ///< External reset. +#define RSTC_KEY 0xA5000000 ///< Password. +/*\}*/ + +/** Reset Controller Status Register */ +/*\{*/ +#define RSTC_SR (*((volatile uint32_t *)(RSTC_BASE + 0x04))) ///< Reset controller status register address. +#define RSTC_URSTS 0 ///< User reset status. +#define RSTC_BODSTS 1 ///< Brownout detection status. +#define RSTC_RSTTYP_MASK 0x00000700 ///< Reset type. +#define RSTC_RSTTYP_POWERUP 0x00000000 ///< Power-up reset. +//#define RSTC_RSTTYP_WAKEUP 0x00000100 ///< VDDCORE rising. +#define RSTC_RSTTYP_WATCHDOG 0x00000200 ///< Watchdog reset. +#define RSTC_RSTTYP_SOFTWARE 0x00000300 ///< Software reset. +#define RSTC_RSTTYP_USER 0x00000400 ///< User reset. +#define RSTC_RSTTYP_BROWNOUT 0x00000500 ///< Brownout reset. +#define RSTC_NRSTL 16 ///< NRST pin level. +#define RSTC_SRCMP 17 ///< Software reset command in progress. +/*\}*/ + +/** Reset Controller Mode Register */ +/*\{*/ +#define RSTC_MR (*((volatile uint32_t *)(RSTC_BASE + 0x08))) ///< Reset controller mode register address. +#define RSTC_URSTEN 0 ///< User reset enable. +#define RSTC_URSTIEN 4 ///< User reset interrupt enable. +#define RSTC_ERSTL_MASK 0x00000F00 ///< External reset length. +#define RSTC_ERSTL_SHIFT 8 ///< Least significant bit of external reset length. +#define RSTC_BODIEN 16 ///< Brown-out detection interrupt enable. +/*\}*/ + + +#endif /* AT91_RTSC_H */ diff --git a/cpu/arm/io/at91_wdt.h b/cpu/arm/io/at91_wdt.h new file mode 100644 index 00000000..093e7a6d --- /dev/null +++ b/cpu/arm/io/at91_wdt.h @@ -0,0 +1,111 @@ +/** + * \file + * + * + * \version $Id$ + * + * \author Francesco Sacchi + * + * AT91 Watchdog. + * This file is based on NUT/OS implementation. See license below. + */ + + +/* + * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE + * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * For additional information see http://www.ethernut.de/ + */ + +#ifndef AT91_WDT_H +#define AT91_WDT_H + + +/** Watch Dog Control Register */ +/*\{*/ +#define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset. +#define WDT_CR (*((volatile uint32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address. +#define WDT_WDRSTT 0 ///< Watchdog restart. +#define WDT_KEY 0xA5000000 ///< Watchdog password. +/*\}*/ + +/** Watch Dog Mode Register */ +/*\{*/ +#define WDT_MR_OFF 0x00000004 ///< Mode register offset. +#define WDT_MR (*((volatile uint32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address. +#define WDT_WDV_MASK 0x00000FFF ///< Counter value mask. +#define WDT_WDV_SHIFT 0 ///< Counter value LSB. +#define WDT_WDFIEN 12 ///< Fault interrupt enable. +#define WDT_WDRSTEN 13 ///< Reset enable. +#define WDT_WDRPROC 14 ///< Eset processor enable. +#define WDT_WDDIS 15 ///< Watchdog disable. +#define WDT_WDD_MASK 0x0FFF0000 ///< Delta value mask. +#define WDT_WDD_SHIFT 16 ///< Delta value LSB. +#define WDT_WDDBGHLT 28 ///< Watchdog debug halt. +#define WDT_WDIDLEHLT 29 ///< Watchdog idle halt. +/*\}*/ + +/** Watch Dog Status Register */ +/*\{*/ +#define WDT_SR_OFF 0x00000008 ///< Status register offset. +#define WDT_SR (*((volatile uint32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address. +#define WDT_WDUNF 0 ///< Watchdog underflow. +#define WDT_WDERR 1 ///< Watchdog error. +/*\}*/ + + +#endif /* AT91_WDT_H */ diff --git a/cpu/arm/io/at91sam7s.h b/cpu/arm/io/at91sam7s.h index c3b93ca0..073ca075 100644 --- a/cpu/arm/io/at91sam7s.h +++ b/cpu/arm/io/at91sam7s.h @@ -100,6 +100,9 @@ #include "at91_aic.h" #include "at91_pit.h" #include "at91_pmc.h" +#include "at91_mc.h" +#include "at91_wdt.h" +#include "at91_rstc.h" //TODO: add other peripherals /** Peripheral Identifiers and Interrupts */ -- 2.25.1