From 15266a01cf4b9b542f445af6551f9e4e78d81dcd Mon Sep 17 00:00:00 2001
From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Fri, 10 Sep 2010 09:05:39 +0000
Subject: [PATCH] Move some specific lm3s clock definition to its init module.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4226 38d2e660-2303-0410-9eaa-f027e97ec537
---
 bertos/cpu/cortex-m3/drv/clock_lm3s.c | 21 ++++++++++++++++++
 bertos/cpu/cortex-m3/hw/init_cm3.c    | 32 ++++++---------------------
 2 files changed, 28 insertions(+), 25 deletions(-)

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index df4681ea..0c79f878 100644
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -97,6 +97,27 @@ void clock_init(void)
 	unsigned long clk;
 	int i;
 
+	/*
+	 * PLL may not function properly at default LDO setting.
+	 *
+	 * Description:
+	 *
+	 * In designs that enable and use the PLL module, unstable device
+	 * behavior may occur with the LDO set at its default of 2.5 volts or
+	 * below (minimum of 2.25 volts). Designs that do not use the PLL
+	 * module are not affected.
+	 *
+	 * Workaround: Prior to enabling the PLL module, it is recommended that
+	 * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
+	 * the LDO Power Control (LDOPCTL) register.
+	 *
+	 * Silicon Revision Affected: A1, A2
+	 *
+	 * See also: Stellaris LM3S1968 A2 Errata documentation.
+	 */
+	if (REVISION_IS_A1 | REVISION_IS_A2)
+		HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
+
 	rcc = HWREG(SYSCTL_RCC);
 	rcc2 = HWREG(SYSCTL_RCC2);
 
diff --git a/bertos/cpu/cortex-m3/hw/init_cm3.c b/bertos/cpu/cortex-m3/hw/init_cm3.c
index 8415cbfb..65009d35 100644
--- a/bertos/cpu/cortex-m3/hw/init_cm3.c
+++ b/bertos/cpu/cortex-m3/hw/init_cm3.c
@@ -35,15 +35,19 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */
+#include "switch_ctx_cm3.h"
+
 #include <cfg/compiler.h>
-#include <cfg/cfg_proc.h> /* CONFIG_KERN_PREEMPT */
-#include <kern/proc_p.h>
 #include <cfg/debug.h>
+
 #include <cpu/attr.h> /* PAUSE */
 #include <cpu/irq.h> /* IRQ_DISABLE */
 #include <cpu/types.h>
+
 #include <drv/irq_cm3.h>
-#include "switch_ctx_cm3.h"
+
+#include <kern/proc_p.h>
 
 #if CPU_CM3_LM3S
 #include <drv/clock_lm3s.h>
@@ -65,28 +69,6 @@ void __init2(void)
 	 */
 	IRQ_DISABLE;
 
-#if CPU_CM3_LM3S
-	/*
-	 * PLL may not function properly at default LDO setting.
-	 *
-	 * Description:
-	 *
-	 * In designs that enable and use the PLL module, unstable device
-	 * behavior may occur with the LDO set at its default of 2.5 volts or
-	 * below (minimum of 2.25 volts). Designs that do not use the PLL
-	 * module are not affected.
-	 *
-	 * Workaround: Prior to enabling the PLL module, it is recommended that
-	 * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
-	 * the LDO Power Control (LDOPCTL) register.
-	 *
-	 * Silicon Revision Affected: A1, A2
-	 *
-	 * See also: Stellaris LM3S1968 A2 Errata documentation.
-	 */
-	if (REVISION_IS_A1 | REVISION_IS_A2)
-		HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
-#endif
 	/* Set the appropriate clocking configuration */
 	clock_init();
 
-- 
2.25.1