From 2600c0780d6203575503c2f1768582c5c0865670 Mon Sep 17 00:00:00 2001 From: batt Date: Thu, 18 Oct 2007 11:07:03 +0000 Subject: [PATCH] Use reg32_t for registers. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@899 38d2e660-2303-0410-9eaa-f027e97ec537 --- cpu/arm/io/at91.h | 4 +- cpu/arm/io/at91_aic.h | 34 +++++++------- cpu/arm/io/at91_mc.h | 12 ++--- cpu/arm/io/at91_pio.h | 8 ++-- cpu/arm/io/at91_pit.h | 8 ++-- cpu/arm/io/at91_pmc.h | 34 +++++++------- cpu/arm/io/at91_rstc.h | 6 +-- cpu/arm/io/at91_us.h | 98 +++++++++++++++++++-------------------- cpu/arm/io/at91_wdt.h | 6 +-- cpu/arm/io/at91sam7s256.h | 8 ++-- 10 files changed, 110 insertions(+), 108 deletions(-) diff --git a/cpu/arm/io/at91.h b/cpu/arm/io/at91.h index c16bfdf4..840fb59a 100644 --- a/cpu/arm/io/at91.h +++ b/cpu/arm/io/at91.h @@ -77,7 +77,7 @@ /** * Interrupt entry point. - * Needed because AT91 uses an Interrupt Controlled with auto-vectoring. + * Needed because AT91 uses an Interrupt Controller with auto-vectoring. */ #define IRQ_ENTRY() \ asm volatile("sub lr, lr,#4" "\n\t" /* Adjust LR */ \ @@ -87,7 +87,7 @@ /** * Interrupt exit. - * Needed because AT91 uses an Interrupt Controlled with auto-vectoring. + * Needed because AT91 uses an Interrupt Controller with auto-vectoring. */ #define IRQ_EXIT() \ asm volatile("ldmfd sp!, {r1}" "\n\t" /* Restore SPSR */ \ diff --git a/cpu/arm/io/at91_aic.h b/cpu/arm/io/at91_aic.h index b85f28b6..8fdd2914 100644 --- a/cpu/arm/io/at91_aic.h +++ b/cpu/arm/io/at91_aic.h @@ -80,7 +80,7 @@ /** * Source mode register array. */ -#define AIC_SMR(i) (*((volatile uint32_t *)(AIC_BASE + (i) * 4))) +#define AIC_SMR(i) (*((reg32_t *)(AIC_BASE + (i) * 4))) /** * Priority mask. @@ -124,38 +124,38 @@ typedef void (*irq_handler_t)(void); /** Interrupt Vector Register */ /*\{*/ #define AIC_IVR_OFF 0x00000100 ///< IRQ vector register offset. -#define AIC_IVR (*((volatile uint32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address. +#define AIC_IVR (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address. /*\}*/ /** Fast Interrupt Vector Register */ /*\{*/ #define AIC_FVR_OFF 0x00000104 ///< FIQ vector register offset. -#define AIC_FVR (*((volatile uint32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address. +#define AIC_FVR (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address. /*\}*/ /** Interrupt Status Register */ /*\{*/ #define AIC_ISR_OFF 0x00000108 ///< Interrupt status register offset. -#define AIC_ISR (*((volatile uint32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address. +#define AIC_ISR (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address. #define AIC_IRQID_MASK 0x0000001F ///< Current interrupt identifier mask. /*\}*/ /** Interrupt Pending Register */ /*\{*/ #define AIC_IPR_OFF 0x0000010C ///< Interrupt pending register offset. -#define AIC_IPR (*((volatile uint32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address. +#define AIC_IPR (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address. /*\}*/ /** Interrupt Mask Register */ /*\{*/ #define AIC_IMR_OFF 0x00000110 ///< Interrupt mask register offset. -#define AIC_IMR (*((volatile uint32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address. +#define AIC_IMR (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address. /*\}*/ /** Interrupt Core Status Register */ /*\{*/ #define AIC_CISR_OFF 0x00000114 ///< Core interrupt status register offset. -#define AIC_CISR (*((volatile uint32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address. +#define AIC_CISR (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address. #define AIC_NFIQ 1 ///< Core FIQ Status #define AIC_NIRQ 2 ///< Core IRQ Status /*\}*/ @@ -163,61 +163,61 @@ typedef void (*irq_handler_t)(void); /** Interrupt Enable Command Register */ /*\{*/ #define AIC_IECR_OFF 0x00000120 ///< Interrupt enable command register offset. -#define AIC_IECR (*((volatile uint32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address. +#define AIC_IECR (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address. /*\}*/ /** Interrupt Disable Command Register */ /*\{*/ #define AIC_IDCR_OFF 0x00000124 ///< Interrupt disable command register offset. -#define AIC_IDCR (*((volatile uint32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address. +#define AIC_IDCR (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address. /*\}*/ /** Interrupt Clear Command Register */ /*\{*/ #define AIC_ICCR_OFF 0x00000128 ///< Interrupt clear command register offset. -#define AIC_ICCR (*((volatile uint32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address. +#define AIC_ICCR (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address. /*\}*/ /** Interrupt Set Command Register */ /*\{*/ #define AIC_ISCR_OFF 0x0000012C ///< Interrupt set command register offset. -#define AIC_ISCR (*((volatile uint32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address. +#define AIC_ISCR (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address. /*\}*/ /** End Of Interrupt Command Register */ /*\{*/ #define AIC_EOICR_OFF 0x00000130 ///< End of interrupt command register offset. -#define AIC_EOICR (*((volatile uint32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address. +#define AIC_EOICR (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address. /*\}*/ /** Spurious Interrupt Vector Register */ /*\{*/ #define AIC_SPU_OFF 0x00000134 ///< Spurious vector register offset. -#define AIC_SPU (*((volatile uint32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address. +#define AIC_SPU (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address. /*\}*/ /** Debug Control Register */ /*\{*/ #define AIC_DCR_OFF 0x0000138 ///< Debug control register offset. -#define AIC_DCR (*((volatile uint32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address. +#define AIC_DCR (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address. /*\}*/ /** Fast Forcing Enable Register */ /*\{*/ #define AIC_FFER_OFF 0x00000140 ///< Fast forcing enable register offset. -#define AIC_FFER (*((volatile uint32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address. +#define AIC_FFER (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address. /*\}*/ /** Fast Forcing Disable Register */ /*\{*/ #define AIC_FFDR_OFF 0x00000144 ///< Fast forcing disable register address. -#define AIC_FFDR (*((volatile uint32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address. +#define AIC_FFDR (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address. /*\}*/ /** Fast Forcing Status Register */ /*\{*/ #define AIC_FFSR_OFF 0x00000148 ///< Fast forcing status register address. -#define AIC_FFSR (*((volatile uint32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address. +#define AIC_FFSR (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address. /*\}*/ #endif /* AT91_AIC_H */ diff --git a/cpu/arm/io/at91_mc.h b/cpu/arm/io/at91_mc.h index c613c8bf..fbae705e 100644 --- a/cpu/arm/io/at91_mc.h +++ b/cpu/arm/io/at91_mc.h @@ -74,11 +74,11 @@ #define AT91_MC_H #define MC_RCR_OFF 0x00000000 ///< MC remap control register offset. -#define MC_RCR (*((volatile uint32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address. +#define MC_RCR (*((reg32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address. #define MC_RCB 0 ///< Remap command. #define MC_ASR_OFF 0x00000004 ///< MC abort status register offset. -#define MC_ASR (*((volatile uint32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address. +#define MC_ASR (*((reg32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address. #define MC_UNDADD 0 ///< Undefined Addess Abort status. #define MC_MISADD 1 ///< Misaligned Addess Abort status. #define MC_ABTSZ_MASK 0x00000300 ///< Abort size status mask. @@ -95,10 +95,10 @@ #define MC_SVMST_ARM 0x04000000 ///< Saved ARM abort source. #define MC_AASR_OFF 0x00000008 ///< MC abort address status register offset. -#define MC_AASR (*((volatile uint32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address. +#define MC_AASR (*((reg32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address. #define MC_FMR_OFF 0x00000060 ///< MC flash mode register offset. -#define MC_FMR (*((volatile uint32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address. +#define MC_FMR (*((reg32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address. #define MC_FRDY 0 ///< Flash ready. #define MC_LOCKE 2 ///< Lock error. #define MC_PROGE 3 ///< Programming error. @@ -111,7 +111,7 @@ #define MC_FMCN_MASK 0x00FF0000 ///< Flash microsecond cycle number mask. #define MC_FCR_OFF 0x00000064 ///< MC flash command register offset. -#define MC_FCR (*((volatile uint32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address. +#define MC_FCR (*((reg32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address. #define MC_FCMD_MASK 0x0000000F ///< Flash command mask. #define MC_FCMD_NOP 0x00000000 ///< No command. #define MC_FCMD_WP 0x00000001 ///< Write page. @@ -126,7 +126,7 @@ #define MC_KEY 0x5A000000 ///< Writing protect key. #define MC_FSR_OFF 0x00000068 ///< MC flash status register offset. -#define MC_FSR (*((volatile uint32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address. +#define MC_FSR (*((reg32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address. #define MC_SECURITY 4 ///< Security bit status. #define MC_GPNVM0 8 ///< General purpose NVM bit 0. diff --git a/cpu/arm/io/at91_pio.h b/cpu/arm/io/at91_pio.h index c9534452..3aa47565 100644 --- a/cpu/arm/io/at91_pio.h +++ b/cpu/arm/io/at91_pio.h @@ -117,7 +117,7 @@ /** Single PIO Register Addresses */ /*\{*/ #if defined(PIO_BASE) - #define PIO_ACCESS(offset) (*((volatile uint32_t *)(PIO_BASE + (offset)))) + #define PIO_ACCESS(offset) (*((reg32_t *)(PIO_BASE + (offset)))) #define PIO_PER PIO_ACCESS(PIO_PER_OFF) ///< PIO enable register address. #define PIO_PDR PIO_ACCESS(PIO_PDR_OFF) ///< PIO disable register address. @@ -162,7 +162,7 @@ /** PIO A Register Addresses */ /*\{*/ #if defined(PIOA_BASE) - #define PIOA_ACCESS(offset) (*((volatile uint32_t *)(PIOA_BASE + (offset)))) + #define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset)))) #define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address. #define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address. @@ -207,7 +207,7 @@ /** PIO B Register Addresses */ /*\{*/ #if defined(PIOB_BASE) - #define PIOB_ACCESS(offset) (*((volatile uint32_t *)(PIOB_BASE + (offset)))) + #define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset)))) #define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address. #define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address. @@ -252,7 +252,7 @@ /** PIO C Register Addresses */ /*\{*/ #if defined(PIOC_BASE) - #define PIOC_ACCESS(offset) (*((volatile uint32_t *)(PIOC_BASE + (offset)))) + #define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset)))) #define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address. #define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address. diff --git a/cpu/arm/io/at91_pit.h b/cpu/arm/io/at91_pit.h index 7e022dce..9bfc3f98 100644 --- a/cpu/arm/io/at91_pit.h +++ b/cpu/arm/io/at91_pit.h @@ -79,7 +79,7 @@ *\{ */ #define PIT_MR_OFF 0x00000000 ///< Mode register offset. -#define PIT_MR (*((volatile uint32_t *)(PIT_BASE + PIT_MR_OFF))) ///< Mode register address. +#define PIT_MR (*((reg32_t *)(PIT_BASE + PIT_MR_OFF))) ///< Mode register address. #define PIV_MASK 0x000FFFFF ///< Periodic interval value mask. #define PIV_SHIFT 0 ///< Periodic interval value shift. @@ -92,7 +92,7 @@ *\{ */ #define PIT_SR_OFF 0x00000004 ///< Status register offset. -#define PIT_SR (*((volatile uint32_t *)(PIT_BASE + PIT_SR_OFF))) ///< Status register address. +#define PIT_SR (*((reg32_t *)(PIT_BASE + PIT_SR_OFF))) ///< Status register address. #define PITS 0 ///< Timer has reached PIV. /*\}*/ @@ -102,10 +102,10 @@ *\{ */ #define PIVR_OFF 0x00000008 ///< Value register offset. -#define PIVR (*((volatile uint32_t *)(PIT_BASE + PIVR_OFF))) ///< Value register address. +#define PIVR (*((reg32_t *)(PIT_BASE + PIVR_OFF))) ///< Value register address. #define PIIR_OFF 0x0000000C ///< Image register offset. -#define PIIR (*((volatile uint32_t *)(PIT_BASE + PIIR_OFF))) ///< Image register address. +#define PIIR (*((reg32_t *)(PIT_BASE + PIIR_OFF))) ///< Image register address. #define CPIV_MASK 0x000FFFFF ///< Current periodic interval value mask. #define CPIV_SHIFT 0 ///< Current periodic interval value SHIFT. #define PICNT_MASK 0xFFF00000 ///< Periodic interval counter mask. diff --git a/cpu/arm/io/at91_pmc.h b/cpu/arm/io/at91_pmc.h index 35ecd766..b7d5b4f5 100644 --- a/cpu/arm/io/at91_pmc.h +++ b/cpu/arm/io/at91_pmc.h @@ -76,11 +76,11 @@ /** System Clock Enable, Disable and Status Register */ /*\{*/ #define PMC_SCER_OFF 0x00000000 ///< System clock enable register offset. -#define PMC_SCER (*((volatile uint32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System clock enable register address. +#define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System clock enable register address. #define PMC_SCDR_OFF 0x00000004 ///< System clock disable register offset. -#define PMC_SCDR (*((volatile uint32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System clock disable register address. +#define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System clock disable register address. #define PMC_SCSR_OFF 0x00000008 ///< System clock status register offset. -#define PMC_SCSR (*((volatile uint32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System clock status register address. +#define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System clock status register address. #define PMC_PCK 0 ///< Processor clock. #define PMC_UDP 7 ///< USB device port clock. @@ -92,17 +92,17 @@ /** Peripheral Clock Enable, Disable and Status Register */ /*\{*/ #define PMC_PCER_OFF 0x00000010 ///< Peripheral clock enable register offset. -#define PMC_PCER (*((volatile uint32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral clock enable register address. +#define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral clock enable register address. #define PMC_PCDR_OFF 0x00000014 ///< Peripheral clock disable register offset. -#define PMC_PCDR (*((volatile uint32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral clock disable register address. +#define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral clock disable register address. #define PMC_PCSR_OFF 0x00000018 ///< Peripheral clock status register offset. -#define PMC_PCSR (*((volatile uint32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral clock status register address. +#define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral clock status register address. /*\}*/ /** Clock Generator Main Oscillator Register */ /*\{*/ #define CKGR_MOR_OFF 0x00000020 ///< Main oscillator register offset. -#define CKGR_MOR (*((volatile uint32_t *)(PMC_BASE + CKGR_MOR_OFF))) ///< Main oscillator register address. +#define CKGR_MOR (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF))) ///< Main oscillator register address. #define CKGR_MOSCEN 0 ///< Main oscillator enable. #define CKGR_OSCBYPASS 1 ///< Main oscillator bypass. @@ -113,7 +113,7 @@ /** Clock Generator Main Clock Frequency Register */ /*\{*/ #define CKGR_MCFR_OFF 0x00000024 ///< Main clock frequency register offset. -#define CKGR_MCFR (*((volatile uint32_t *)(PMC_BASE + CKGR_MCFR_OFF))) ///< Main clock frequency register address. +#define CKGR_MCFR (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF))) ///< Main clock frequency register address. #define CKGR_MAINF_MASK 0x0000FFFF ///< Main clock frequency mask mask. #define CKGR_MAINRDY 16 ///< Main clock ready. @@ -122,7 +122,7 @@ /** PLL Registers */ /*\{*/ #define CKGR_PLLR_OFF 0x0000002C ///< Clock generator PLL register offset. -#define CKGR_PLLR (*((volatile uint32_t *)(PMC_BASE + CKGR_PLLR_OFF))) ///< Clock generator PLL register address. +#define CKGR_PLLR (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF))) ///< Clock generator PLL register address. #define CKGR_DIV_MASK 0x000000FF ///< Divider. #define CKGR_DIV_SHIFT 0 ///< Least significant bit of the divider. @@ -148,14 +148,14 @@ /** Master Clock Register */ /*\{*/ #define PMC_MCKR_OFF 0x00000030 ///< Master clock register offset. -#define PMC_MCKR (*((volatile uint32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master clock register address. +#define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master clock register address. #define PMC_PCKR0_OFF 0x00000040 ///< Programmable clock 0 register offset. -#define PMC_PCKR0 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR0_OFF))) ///< Programmable clock 0 register address. +#define PMC_PCKR0 (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF))) ///< Programmable clock 0 register address. #define PMC_PCKR1_OFF 0x00000044 ///< Programmable clock 1 register offset. -#define PMC_PCKR1 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR1_OFF))) ///< Programmable clock 1 register address. +#define PMC_PCKR1 (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF))) ///< Programmable clock 1 register address. #define PMC_PCKR2_OFF 0x00000048 ///< Programmable clock 2 register offset. -#define PMC_PCKR2 (*((volatile uint32_t *)(PMC_BASE + PMC_PCKR2_OFF))) ///< Programmable clock 2 register address. +#define PMC_PCKR2 (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF))) ///< Programmable clock 2 register address. #define PMC_CSS_MASK 0x00000003 ///< Clock selection mask. #define PMC_CSS_SLOW_CLK 0x00000000 ///< Slow clock selected. @@ -176,13 +176,13 @@ /** Power Management Status and Interrupt Registers */ /*\{*/ #define PMC_IER_OFF 0x00000060 ///< Interrupt enable register offset. -#define PMC_IER (*((volatile uint32_t *)(PMC_BASE + PMC_IER_OFF))) ///< Interrupt enable register address. +#define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF))) ///< Interrupt enable register address. #define PMC_IDR_OFF 0x00000064 ///< Interrupt disable register offset. -#define PMC_IDR (*((volatile uint32_t *)(PMC_BASE + PMC_IDR_OFF))) ///< Interrupt disable register address. +#define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF))) ///< Interrupt disable register address. #define PMC_SR_OFF 0x00000068 ///< Status register offset. -#define PMC_SR (*((volatile uint32_t *)(PMC_BASE + PMC_SR_OFF))) ///< Status register address. +#define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF))) ///< Status register address. #define PMC_IMR_OFF 0x0000006C ///< Interrupt mask register offset. -#define PMC_IMR (*((volatile uint32_t *)(PMC_BASE + PMC_IMR_OFF))) ///< Interrupt mask register address. +#define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF))) ///< Interrupt mask register address. #define PMC_MOSCS 0 ///< Main oscillator. #define PMC_LOCK 2 ///< PLL lock. diff --git a/cpu/arm/io/at91_rstc.h b/cpu/arm/io/at91_rstc.h index 7e4c1a7a..96be7c34 100644 --- a/cpu/arm/io/at91_rstc.h +++ b/cpu/arm/io/at91_rstc.h @@ -75,7 +75,7 @@ /** Reset Controller Control Register */ /*\{*/ -#define RSTC_CR (*((volatile uint32_t *)(RSTC_BASE + 0x00))) ///< Reset controller control register address. +#define RSTC_CR (*((reg32_t *)(RSTC_BASE + 0x00))) ///< Reset controller control register address. #define RSTC_PROCRST 0 ///< Processor reset. #define RSTC_PERRST 2 ///< Peripheral reset. #define RSTC_EXTRST 3 ///< External reset. @@ -84,7 +84,7 @@ /** Reset Controller Status Register */ /*\{*/ -#define RSTC_SR (*((volatile uint32_t *)(RSTC_BASE + 0x04))) ///< Reset controller status register address. +#define RSTC_SR (*((reg32_t *)(RSTC_BASE + 0x04))) ///< Reset controller status register address. #define RSTC_URSTS 0 ///< User reset status. #define RSTC_BODSTS 1 ///< Brownout detection status. #define RSTC_RSTTYP_MASK 0x00000700 ///< Reset type. @@ -100,7 +100,7 @@ /** Reset Controller Mode Register */ /*\{*/ -#define RSTC_MR (*((volatile uint32_t *)(RSTC_BASE + 0x08))) ///< Reset controller mode register address. +#define RSTC_MR (*((reg32_t *)(RSTC_BASE + 0x08))) ///< Reset controller mode register address. #define RSTC_URSTEN 0 ///< User reset enable. #define RSTC_URSTIEN 4 ///< User reset interrupt enable. #define RSTC_ERSTL_MASK 0x00000F00 ///< External reset length. diff --git a/cpu/arm/io/at91_us.h b/cpu/arm/io/at91_us.h index 5271dfea..4015ae4b 100644 --- a/cpu/arm/io/at91_us.h +++ b/cpu/arm/io/at91_us.h @@ -77,8 +77,8 @@ */ /*\{*/ #define US_CR_OFF 0x00000000 ///< USART control register offset. -#define US0_CR (*((volatile uint32_t *)(USART0_BASE + US_CR_OFF) ///< Channel 0 control register address. -#define US1_CR (*((volatile uint32_t *)(USART1_BASE + US_CR_OFF) ///< Channel 1 control register address. +#define US0_CR (*((reg32_t *)(USART0_BASE + US_CR_OFF) ///< Channel 0 control register address. +#define US1_CR (*((reg32_t *)(USART1_BASE + US_CR_OFF) ///< Channel 1 control register address. #define US_RSTRX 2 ///< Reset receiver. */ #define US_RSTTX 3 ///< Reset transmitter. #define US_RXEN 4 ///< Receiver enable. @@ -104,8 +104,8 @@ */ /*\{*/ #define US_MR_OFF 0x00000004 ///< USART mode register offset. -#define US0_MR (*((volatile uint32_t *)(USART0_BASE + US_MR_OFF) ///< Channel 0 mode register address. -#define US1_MR (*((volatile uint32_t *)(USART1_BASE + US_MR_OFF) ///< Channel 1 mode register address. +#define US0_MR (*((reg32_t *)(USART0_BASE + US_MR_OFF) ///< Channel 0 mode register address. +#define US1_MR (*((reg32_t *)(USART1_BASE + US_MR_OFF) ///< Channel 1 mode register address. #define US_USART_MODE_MASK 0x0000000F ///< USART mode mask. #define US_USART_MODE_NORMA 0x00000000 ///< Normal. @@ -167,20 +167,20 @@ */ /*\{*/ #define US_IER_OFF 0x00000008 ///< USART interrupt enable register offset. -#define US0_IER (*((volatile uint32_t *)(USART0_BASE + US_IER_OFF) ///< Channel 0 interrupt enable register address. -#define US1_IER (*((volatile uint32_t *)(USART1_BASE + US_IER_OFF) ///< Channel 1 interrupt enable register address. +#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF) ///< Channel 0 interrupt enable register address. +#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF) ///< Channel 1 interrupt enable register address. #define US_IDR_OFF 0x0000000C ///< USART interrupt disable register offset. -#define US0_IDR (*((volatile uint32_t *)(USART0_BASE + US_IDR_OFF) ///< Channel 0 interrupt disable register address. -#define US1_IDR (*((volatile uint32_t *)(USART1_BASE + US_IDR_OFF) ///< Channel 1 interrupt disable register address. +#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF) ///< Channel 0 interrupt disable register address. +#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF) ///< Channel 1 interrupt disable register address. #define US_IMR_OFF 0x00000010 ///< USART interrupt mask register offset. -#define US0_IMR (*((volatile uint32_t *)(USART0_BASE + US_IMR_OFF) ///< Channel 0 interrupt mask register address. -#define US1_IMR (*((volatile uint32_t *)(USART1_BASE + US_IMR_OFF) ///< Channel 1 interrupt mask register address. +#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF) ///< Channel 0 interrupt mask register address. +#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF) ///< Channel 1 interrupt mask register address. #define US_CSR_OFF 0x00000014 ///< USART status register offset. -#define US0_CSR (*((volatile uint32_t *)(USART0_BASE + US_CSR_OFF) ///< Channel 0 status register address. -#define US1_CSR (*((volatile uint32_t *)(USART1_BASE + US_CSR_OFF) ///< Channel 1 status register address. +#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF) ///< Channel 0 status register address. +#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF) ///< Channel 1 status register address. #define US_CSR_RI 20 ///< Image of RI input. #define US_CSR_DSR 21 ///< Image of DSR input. #define US_CSR_DCD 22 ///< Image of DCD input. @@ -210,8 +210,8 @@ */ /*\{*/ #define US_RHR_OFF 0x00000018 ///< USART receiver holding register offset. -#define US0_RHR (*((volatile uint32_t *)(USART0_BASE + US_RHR_OFF) ///< Channel 0 receiver holding register address. -#define US1_RHR (*((volatile uint32_t *)(USART1_BASE + US_RHR_OFF) ///< Channel 1 receiver holding register address. +#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF) ///< Channel 0 receiver holding register address. +#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF) ///< Channel 1 receiver holding register address. #define US_RHR_RXCHR_MASK 0x000001FF ///< Last char received if US_RXRDY is set. #define US_RHR_RXSYNH 15 ///< Received sync. /*\}*/ @@ -221,8 +221,8 @@ */ /*\{*/ #define US_THR_OFF 0x0000001C ///< USART transmitter holding register offset. -#define US0_THR (*((volatile uint32_t *)(USART0_BASE + US_THR_OFF) ///< Channel 0 transmitter holding register address. -#define US1_THR (*((volatile uint32_t *)(USART1_BASE + US_THR_OFF) ///< Channel 1 transmitter holding register address. +#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF) ///< Channel 0 transmitter holding register address. +#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF) ///< Channel 1 transmitter holding register address. #define US_THR_TXCHR_MASK 0x000001FF ///< Next char to be trasmitted. #define US_THR_TXSYNH 15 ///< Sync field to be trasmitted. /*\}*/ @@ -232,8 +232,8 @@ */ /*\{*/ #define US_BRGR_OFF 0x00000020 ///< USART baud rate register offset. -#define US0_BRGR (*((volatile uint32_t *)(USART0_BASE + US_BRGR_OFF) ///< Channel 0 baud rate register address. -#define US1_BRGR (*((volatile uint32_t *)(USART1_BASE + US_BRGR_OFF) ///< Channel 1 baud rate register address. +#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF) ///< Channel 0 baud rate register address. +#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF) ///< Channel 1 baud rate register address. #define US_BRGR_MASK 0x0000FFFF ///< Clock divider. #define US_BRGR_FP_MASK 0x001F0000 ///< Fractional part. /*\}*/ @@ -243,8 +243,8 @@ */ /*\{*/ #define US_RTOR_OFF 0x00000024 ///< USART receiver timeout register offset. -#define US0_RTOR (*((volatile uint32_t *)(USART0_BASE + US_RTOR_OFF) ///< Channel 0 receiver timeout register address. -#define US1_RTOR (*((volatile uint32_t *)(USART1_BASE + US_RTOR_OFF) ///< Channel 1 receiver timeout register address. +#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF) ///< Channel 0 receiver timeout register address. +#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF) ///< Channel 1 receiver timeout register address. /*\}*/ /** @@ -252,8 +252,8 @@ */ /*\{*/ #define US_TTGR_OFF 0x00000028 ///< USART transmitter time guard register offset. -#define US0_TTGR (*((volatile uint32_t *)(USART0_BASE + US_TTGR_OFF) ///< Channel 0 transmitter time guard register address. -#define US1_TTGR (*((volatile uint32_t *)(USART1_BASE + US_TTGR_OFF) ///< Channel 1 transmitter time guard register address. +#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF) ///< Channel 0 transmitter time guard register address. +#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF) ///< Channel 1 transmitter time guard register address. /*\}*/ /** @@ -261,8 +261,8 @@ */ /*\{*/ #define US_FIDI_OFF 0x00000040 ///< USART FI DI ratio register offset. -#define US0_FIDI (*((volatile uint32_t *)(USART0_BASE + US_FIDI_OFF) ///< Channel 0 FI DI ratio register address. -#define US1_FIDI (*((volatile uint32_t *)(USART1_BASE + US_FIDI_OFF) ///< Channel 1 FI DI ratio register address. +#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF) ///< Channel 0 FI DI ratio register address. +#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF) ///< Channel 1 FI DI ratio register address. /*\}*/ /** @@ -270,8 +270,8 @@ */ /*\{*/ #define US_NER_OFF 0x00000044 ///< USART error counter register offset. -#define US0_NER (*((volatile uint32_t *)(USART0_BASE + US_NER_OFF) ///< Channel 0 error counter register address. -#define US1_NER (*((volatile uint32_t *)(USART1_BASE + US_NER_OFF) ///< Channel 1 error counter register address. +#define US0_NER (*((reg32_t *)(USART0_BASE + US_NER_OFF) ///< Channel 0 error counter register address. +#define US1_NER (*((reg32_t *)(USART1_BASE + US_NER_OFF) ///< Channel 1 error counter register address. /*\}*/ /** @@ -279,66 +279,66 @@ */ /*\{*/ #define US_IF_OFF 0x0000004C ///< USART IrDA filter register offset. -#define US0_IF (*((volatile uint32_t *)(USART0_BASE + US_IF_OFF) ///< Channel 0 IrDA filter register address. -#define US1_IF (*((volatile uint32_t *)(USART1_BASE + US_IF_OFF) ///< Channel 1 IrDA filter register address. +#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF) ///< Channel 0 IrDA filter register address. +#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF) ///< Channel 1 IrDA filter register address. /*\}*/ -#if defined(*((volatile uint32_t *)(USART_HAS_PDC) +#if defined(*((reg32_t *)(USART_HAS_PDC) /** * Receive Pointer Register */ /*\{*/ -#define US0_RPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RPR_OFF) ///< Channel 0 receive pointer register address. -#define US1_RPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RPR_OFF) ///< Channel 1 receive pointer register address. +#define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF) ///< Channel 0 receive pointer register address. +#define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF) ///< Channel 1 receive pointer register address. /*\}*/ /** * Receive Counter Register */ /*\{*/ -#define US0_RCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RCR_OFF) ///< Channel 0 receive counter register address. -#define US1_RCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RCR_OFF) ///< Channel 1 receive counter register address. +#define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF) ///< Channel 0 receive counter register address. +#define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF) ///< Channel 1 receive counter register address. /*\}*/ /** * Transmit Pointer Register */ /*\{*/ -#define US0_TPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TPR_OFF) ///< Channel 0 transmit pointer register address. -#define US1_TPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TPR_OFF) ///< Channel 1 transmit pointer register address. +#define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF) ///< Channel 0 transmit pointer register address. +#define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF) ///< Channel 1 transmit pointer register address. /*\}*/ /** * Name Transmit Counter Register */ /*\{*/ -#define US0_TCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TCR_OFF) ///< Channel 0 transmit counter register address. -#define US1_TCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TCR_OFF) ///< Channel 1 transmit counter register address. +#define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF) ///< Channel 0 transmit counter register address. +#define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF) ///< Channel 1 transmit counter register address. /*\}*/ #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF) -#define US0_RNPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RNPR_OFF) ///< PDC channel 0 receive next pointer register. -#define US1_RNPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RNPR_OFF) ///< PDC channel 1 receive next pointer register. -#define US0_RNCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_RNCR_OFF) ///< PDC channel 0 receive next counter register. -#define US1_RNCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_RNCR_OFF) ///< PDC channel 1 receive next counter register. +#define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF) ///< PDC channel 0 receive next pointer register. +#define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF) ///< PDC channel 1 receive next pointer register. +#define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF) ///< PDC channel 0 receive next counter register. +#define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF) ///< PDC channel 1 receive next counter register. #endif #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF) -#define US0_TNPR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TNPR_OFF) ///< PDC channel 0 transmit next pointer register. -#define US1_TNPR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TNPR_OFF) ///< PDC channel 1 transmit next pointer register. -#define US0_TNCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_TNCR_OFF) ///< PDC channel 0 transmit next counter register. -#define US1_TNCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_TNCR_OFF) ///< PDC channel 1 transmit next counter register. +#define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF) ///< PDC channel 0 transmit next pointer register. +#define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF) ///< PDC channel 1 transmit next pointer register. +#define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF) ///< PDC channel 0 transmit next counter register. +#define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF) ///< PDC channel 1 transmit next counter register. #endif #if defined(PERIPH_PTCR_OFF) -#define US0_PTCR (*((volatile uint32_t *)(USART0_BASE + PERIPH_PTCR_OFF) ///< PDC channel 0 transfer control register. -#define US1_PTCR (*((volatile uint32_t *)(USART1_BASE + PERIPH_PTCR_OFF) ///< PDC channel 1 transfer control register. +#define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF) ///< PDC channel 0 transfer control register. +#define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF) ///< PDC channel 1 transfer control register. #endif #if defined(PERIPH_PTSR_OFF) -#define US0_PTSR (*((volatile uint32_t *)(USART0_BASE + PERIPH_PTSR_OFF) ///< PDC channel 0 transfer status register. -#define US1_PTSR (*((volatile uint32_t *)(USART1_BASE + PERIPH_PTSR_OFF) ///< PDC channel 1 transfer status register. +#define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF) ///< PDC channel 0 transfer status register. +#define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF) ///< PDC channel 1 transfer status register. #endif #endif /* USART_HAS_PDC */ diff --git a/cpu/arm/io/at91_wdt.h b/cpu/arm/io/at91_wdt.h index 093e7a6d..ed394665 100644 --- a/cpu/arm/io/at91_wdt.h +++ b/cpu/arm/io/at91_wdt.h @@ -78,7 +78,7 @@ /** Watch Dog Control Register */ /*\{*/ #define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset. -#define WDT_CR (*((volatile uint32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address. +#define WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address. #define WDT_WDRSTT 0 ///< Watchdog restart. #define WDT_KEY 0xA5000000 ///< Watchdog password. /*\}*/ @@ -86,7 +86,7 @@ /** Watch Dog Mode Register */ /*\{*/ #define WDT_MR_OFF 0x00000004 ///< Mode register offset. -#define WDT_MR (*((volatile uint32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address. +#define WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address. #define WDT_WDV_MASK 0x00000FFF ///< Counter value mask. #define WDT_WDV_SHIFT 0 ///< Counter value LSB. #define WDT_WDFIEN 12 ///< Fault interrupt enable. @@ -102,7 +102,7 @@ /** Watch Dog Status Register */ /*\{*/ #define WDT_SR_OFF 0x00000008 ///< Status register offset. -#define WDT_SR (*((volatile uint32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address. +#define WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address. #define WDT_WDUNF 0 ///< Watchdog underflow. #define WDT_WDERR 1 ///< Watchdog error. /*\}*/ diff --git a/cpu/arm/io/at91sam7s256.h b/cpu/arm/io/at91sam7s256.h index 6c22208e..e59733b5 100644 --- a/cpu/arm/io/at91sam7s256.h +++ b/cpu/arm/io/at91sam7s256.h @@ -70,8 +70,10 @@ * For additional information see http://www.ethernut.de/ */ -#ifndef AT91SAM7S_H -#define AT91SAM7S_H +#ifndef AT91SAM7S256_H +#define AT91SAM7S256_H + +#include #define FLASH_BASE 0x100000UL #define RAM_BASE 0x200000UL @@ -356,4 +358,4 @@ #define PB30_PWM3_B 30 /*\}*/ -#endif /* AT91SAM7S_H */ +#endif /* AT91SAM7S256_H */ -- 2.25.1