From 32eebaf8bf80d1ffd417bfe6d2c34e6cd3684f87 Mon Sep 17 00:00:00 2001 From: batt Date: Thu, 16 Apr 2009 18:01:47 +0000 Subject: [PATCH] Add full support for AT91SAM7S64, AT91SAM7S128, AT91SAM7S512, AT91SAM7X512. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@2525 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/arm/drv/adc_at91.h | 4 +- bertos/cpu/arm/drv/ser_at91.c | 18 +-- bertos/cpu/arm/drv/ser_at91.h | 2 +- bertos/cpu/arm/hw/crtat91sam7_rom.S | 2 +- bertos/cpu/arm/info/AT91SAM7S512.cdef | 53 ++++++++ bertos/cpu/arm/info/AT91SAM7S64.cdef | 53 ++++++++ bertos/cpu/arm/info/AT91SAM7X512.cdef | 53 ++++++++ bertos/cpu/arm/io/at91.h | 2 +- bertos/cpu/arm/io/at91_twi.h | 2 +- bertos/cpu/arm/io/at91sam7.h | 36 +++--- bertos/cpu/arm/scripts/at91sam7_512_ram.ld | 143 +++++++++++++++++++++ bertos/cpu/arm/scripts/at91sam7_512_rom.ld | 143 +++++++++++++++++++++ bertos/cpu/arm/scripts/at91sam7_64_ram.ld | 143 +++++++++++++++++++++ bertos/cpu/arm/scripts/at91sam7_64_rom.ld | 143 +++++++++++++++++++++ bertos/cpu/detect.h | 39 +++++- 15 files changed, 802 insertions(+), 34 deletions(-) create mode 100644 bertos/cpu/arm/info/AT91SAM7S512.cdef create mode 100644 bertos/cpu/arm/info/AT91SAM7S64.cdef create mode 100644 bertos/cpu/arm/info/AT91SAM7X512.cdef create mode 100644 bertos/cpu/arm/scripts/at91sam7_512_ram.ld create mode 100644 bertos/cpu/arm/scripts/at91sam7_512_rom.ld create mode 100644 bertos/cpu/arm/scripts/at91sam7_64_ram.ld create mode 100644 bertos/cpu/arm/scripts/at91sam7_64_rom.ld diff --git a/bertos/cpu/arm/drv/adc_at91.h b/bertos/cpu/arm/drv/adc_at91.h index 6c77de0f..f1125980 100644 --- a/bertos/cpu/arm/drv/adc_at91.h +++ b/bertos/cpu/arm/drv/adc_at91.h @@ -69,11 +69,11 @@ * Define PIO controller for enable ADC function. * \{ */ -#if CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X #define ADC_PIO_DISABLE PIOB_PDR #define ADC_PIO_EN_FUNC PIOB_ASR -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define ADC_PIO_DISABLE PIOA_PDR #define ADC_PIO_EN_FUNC PIOA_BSR diff --git a/bertos/cpu/arm/drv/ser_at91.c b/bertos/cpu/arm/drv/ser_at91.c index f060e14f..bc555160 100644 --- a/bertos/cpu/arm/drv/ser_at91.c +++ b/bertos/cpu/arm/drv/ser_at91.c @@ -84,7 +84,7 @@ * * - Disable GPIO on USART0 tx/rx pins */ - #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 + #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X #warning Check USART0 pins! #endif #define SER_UART0_BUS_TXINIT do { \ @@ -124,7 +124,7 @@ * * - Disable GPIO on USART1 tx/rx pins */ - #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128 + #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X #warning Check USART1 pins! #endif #define SER_UART1_BUS_TXINIT do { \ @@ -181,7 +181,7 @@ #define SER_SPI0_BUS_TXCLOSE #endif -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X #ifndef SER_SPI1_BUS_TXINIT /** @@ -231,7 +231,7 @@ static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE]; static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE]; -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE]; static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE]; #endif @@ -261,7 +261,7 @@ struct ArmSerial static void uart0_irq_dispatcher(void); static void uart1_irq_dispatcher(void); static void spi0_irq_handler(void); -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X static void spi1_irq_handler(void); #endif /* @@ -538,7 +538,7 @@ static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT; } -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X /* SPI driver */ static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser)) { @@ -677,7 +677,7 @@ static const struct SerialHardwareVT SPI0_VT = C99INIT(txStart, spi0_starttx), C99INIT(txSending, tx_sending), }; -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X static const struct SerialHardwareVT SPI1_VT = { C99INIT(init, spi1_init), @@ -722,7 +722,7 @@ static struct ArmSerial UARTDescs[SER_CNT] = }, C99INIT(sending, false), }, - #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 + #if CPU_ARM_SAM7X { C99INIT(hw, /**/) { C99INIT(table, &SPI1_VT), @@ -903,7 +903,7 @@ static void spi0_irq_handler(void) } -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X /** * SPI1 interrupt handler */ diff --git a/bertos/cpu/arm/drv/ser_at91.h b/bertos/cpu/arm/drv/ser_at91.h index 66535499..d345a9e9 100644 --- a/bertos/cpu/arm/drv/ser_at91.h +++ b/bertos/cpu/arm/drv/ser_at91.h @@ -73,7 +73,7 @@ enum SER_UART0, SER_UART1, SER_SPI0, -#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256 +#if CPU_ARM_SAM7X SER_SPI1, #endif SER_CNT /**< Number of serial ports */ diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S index 5addc38a..b435a8cb 100644 --- a/bertos/cpu/arm/hw/crtat91sam7_rom.S +++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S @@ -82,7 +82,7 @@ #endif -#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X /** * With a 18.420MHz cristal, master clock is: * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz diff --git a/bertos/cpu/arm/info/AT91SAM7S512.cdef b/bertos/cpu/arm/info/AT91SAM7S512.cdef new file mode 100644 index 00000000..ca8fabe1 --- /dev/null +++ b/bertos/cpu/arm/info/AT91SAM7S512.cdef @@ -0,0 +1,53 @@ +# +#-*- coding: utf-8 -*- +# +# \file +# +# +# Cpu info of the AT91SAM7S512. +# +# This file contain all info for the BeRTOS wizard. +# +# \author Daniele Basile +# +# + +# Import the common settings for the AT91SAM7 family. +include("at91sam7.common") + +# Short description of the cpu. +CPU_DESC += [ "512 Kbytes internal flash memory", + "64 Kbytes internal SRAM memory" ] + +# GCC flags for this cpu. +CPP_FLAGS += [ "-D__ARM_AT91SAM7S512__" ] +LD_FLAGS += [ "-T " + SCRIPT_DIR + "at91sam7_512_rom.ld" ] + diff --git a/bertos/cpu/arm/info/AT91SAM7S64.cdef b/bertos/cpu/arm/info/AT91SAM7S64.cdef new file mode 100644 index 00000000..e76fb92a --- /dev/null +++ b/bertos/cpu/arm/info/AT91SAM7S64.cdef @@ -0,0 +1,53 @@ +# +#-*- coding: utf-8 -*- +# +# \file +# +# +# Cpu info of the AT91SAM7S64. +# +# This file contain all info for the BeRTOS wizard. +# +# \author Daniele Basile +# +# + +# Import the common settings for the AT91SAM7 family. +include("at91sam7.common") + +# Short description of the cpu. +CPU_DESC += [ "64 Kbytes internal flash memory", + "16 Kbytes internal SRAM memory" ] + +# GCC flags for this cpu. +CPP_FLAGS += [ "-D__ARM_AT91SAM7S64__" ] +LD_FLAGS += [ "-T " + SCRIPT_DIR + "at91sam7_64_rom.ld" ] + diff --git a/bertos/cpu/arm/info/AT91SAM7X512.cdef b/bertos/cpu/arm/info/AT91SAM7X512.cdef new file mode 100644 index 00000000..01178560 --- /dev/null +++ b/bertos/cpu/arm/info/AT91SAM7X512.cdef @@ -0,0 +1,53 @@ +# +#-*- coding: utf-8 -*- +# +# \file +# +# +# Cpu info of the AT91SAM7X512. +# +# This file contain all info for the BeRTOS wizard. +# +# \author Daniele Basile +# +# + +# Import the common settings for the AT91SAM7 family. +include("at91sam7.common") + +# Short description of the cpu. +CPU_DESC += [ "512 Kbytes internal flash memory", + "64 Kbytes internal SRAM memory" ] + +# GCC flags for this cpu. +CPP_FLAGS += [ "-D__ARM_AT91SAM7X512__" ] +LD_FLAGS += [ "-T " + SCRIPT_DIR + "at91sam7_512_rom.ld" ] + diff --git a/bertos/cpu/arm/io/at91.h b/bertos/cpu/arm/io/at91.h index 0cbfd8c5..9e350b48 100644 --- a/bertos/cpu/arm/io/at91.h +++ b/bertos/cpu/arm/io/at91.h @@ -75,7 +75,7 @@ #include -#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X #include "at91sam7.h" #else diff --git a/bertos/cpu/arm/io/at91_twi.h b/bertos/cpu/arm/io/at91_twi.h index 1d7be6ab..3fbe7dc9 100644 --- a/bertos/cpu/arm/io/at91_twi.h +++ b/bertos/cpu/arm/io/at91_twi.h @@ -158,7 +158,7 @@ #define TWI_GACC 0x00000020 ///< General call access. */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define TWI_OVRE 6 ///< Overrun error. #define TWI_UNRE 7 ///< Underrun error. #endif diff --git a/bertos/cpu/arm/io/at91sam7.h b/bertos/cpu/arm/io/at91sam7.h index e41ab1c5..dbc6f449 100644 --- a/bertos/cpu/arm/io/at91sam7.h +++ b/bertos/cpu/arm/io/at91sam7.h @@ -76,7 +76,7 @@ #include -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE #define FLASH_BASE 0x100000UL #define RAM_BASE 0x200000UL @@ -100,7 +100,7 @@ #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address. #define MC_BASE 0xFFFFFF00 ///< Memory controller base. - #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 + #if CPU_ARM_SAM7X #define CAN_BASE 0xFFFD0000 ///< PWM controller base address. #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address. #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address. @@ -108,7 +108,7 @@ #define PIOB_BASE 0xFFFFF600 ///< PIO base address. #endif - #if CPU_ARM_AT91SAM7S256 + #if CPU_ARM_SAM7S_LARGE #define SPI_BASE 0xFFFE0000 ///< SPI0 base address. #endif @@ -147,7 +147,7 @@ * Peripheral Identifiers and Interrupts *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE #define FIQ_ID 0 ///< Fast interrupt ID. #define SYSC_ID 1 ///< System controller interrupt. #define US0_ID 6 ///< USART 0 ID. @@ -163,7 +163,7 @@ #define IRQ0_ID 30 ///< External interrupt 0 ID. #define IRQ1_ID 31 ///< External interrupt 1 ID. - #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 + #if CPU_ARM_SAM7X #define PIOA_ID 2 ///< Parallel A I/O controller ID. #define PIOB_ID 3 ///< Parallel B I/O controller ID. #define SPI0_ID 4 ///< Serial peripheral interface 0 ID. @@ -175,7 +175,7 @@ #endif - #if CPU_ARM_AT91SAM7S256 + #if CPU_ARM_SAM7S_LARGE #define PIOA_ID 2 ///< Parallel I/O controller ID. /* ID 3 is reserved */ #define ADC_ID 4 ///< Analog to digital converter ID. @@ -193,14 +193,14 @@ * USART & DEBUG pin names *\{ */ -#if CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7S_LARGE #define RXD0 5 #define TXD0 6 #define RXD1 21 #define TXD1 22 #define DTXD 10 #define DRXD 9 -#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#elif CPU_ARM_SAM7X #define RXD0 0 // PA0 #define TXD0 1 // PA1 #define RXD1 5 // PA5 @@ -216,13 +216,13 @@ * SPI pins name *\{ */ -#if CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7S_LARGE #define SPI0_NPCS0 11 // Same as NSS pin. #define SPI0_MISO 12 #define SPI0_MOSI 13 #define SPI0_SPCK 14 -#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#elif CPU_ARM_SAM7X #define SPI0_NPCS0 12 // Same as NSS pin. PA12 #define SPI0_NPCS1 13 // PA13 #define SPI0_NPCS2 14 // PA14 @@ -249,7 +249,7 @@ * Timer counter pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define TIOA0 23 // PB23 #define TIOB0 24 // PB24 #define TIOA1 25 // PB25 @@ -260,7 +260,7 @@ #define TIO_PIO_PDR PIOB_PDR #define TIO_PIO_ABSR PIOB_ASR -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define TIOA0 0 // PA0 #define TIOB0 1 // PA1 #define TIOA1 15 // PA15 @@ -282,7 +282,7 @@ * PWM pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define PWM0 19 // PB19 #define PWM1 20 // PB20 #define PWM2 21 // PB21 @@ -294,7 +294,7 @@ #define PWM_PIO_OER PIOB_OER #define PWM_PIO_ABSR PIOB_ASR -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define PWM0 11 // PA11 #define PWM1 12 // PA12 #define PWM2 13 // PA13 @@ -316,11 +316,11 @@ * TWI pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define TWD 10 #define TWCK 11 -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define TWD 3 //PA3 #define TWCK 4 //PA4 @@ -332,14 +332,14 @@ * ADC pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define ADTRG 18 // PB18 #define AD0 23 // PB27 #define AD1 24 // PB28 #define AD2 25 // PB29 #define AD3 26 // PB30 -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define ADTRG 18 // PA8 #define AD0 0 // PA17 #define AD1 1 // PA18 diff --git a/bertos/cpu/arm/scripts/at91sam7_512_ram.ld b/bertos/cpu/arm/scripts/at91sam7_512_ram.ld new file mode 100644 index 00000000..66c4f167 --- /dev/null +++ b/bertos/cpu/arm/scripts/at91sam7_512_ram.ld @@ -0,0 +1,143 @@ +/** + * \file + * + * + * \version $Id: sysirq_at91.c 18273 2007-10-11 14:53:02Z batt $ + * + * \author Daniele Basile + * + * \brief Script linker for Atmel AT91SAM7_512 family processors. + * + */ + + +ENTRY(_init) +SEARCH_DIR(.) +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* + * Define memory configuration for AT91SAM7_512 family + */ +MEMORY +{ + rom(rx) : org = 0x00100000, len = 512k + ram(rwx) : org = 0x00200000, len = 64k +} + + +/* + * Define stack size here + */ +FIQ_STACK_SIZE = 0x0100; +IRQ_STACK_SIZE = 0x0100; +ABT_STACK_SIZE = 0x0100; +UND_STACK_SIZE = 0x0100; +SVC_STACK_SIZE = 0x0400; + +/* + * Allocate section memory + */ +SECTIONS +{ + .text : + { + KEEP(*(.vectors)); + . = ALIGN (4); + KEEP(*(.init)); + . = ALIGN (4); + *(.rodata .rodata.*); + . = ALIGN (4); + *(.text .text.*); + . = ALIGN (4); + *(.glue_7t); + . = ALIGN(4); + *(.glue_7); + . = ALIGN(4); + } > ram + + _etext = .; + PROVIDE (__etext = .); + + .data : AT (_etext) + { + PROVIDE (__data_start = .); + *(.data .data.*) + . = ALIGN (4); + _edata = .; + PROVIDE (__data_end = .); + } > ram + + .bss : + { + PROVIDE (__bss_start = .); + *(.bss .bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + } > ram + + /* + * Allocated stack at the end of bss section. + * Data heap is allocate at end of stack. + */ + PROVIDE (__stack_start = .); + + PROVIDE (__stack_fiq_start = .); + . += FIQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_fiq_end = .); + + PROVIDE (__stack_irq_start = .); + . += IRQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_irq_end = .); + + PROVIDE (__stack_abt_start = .); + . += ABT_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_abt_end = .); + + PROVIDE (__stack_und_start = .); + . += UND_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_und_end = .); + + PROVIDE (__stack_svc_start = .); + . += SVC_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_svc_end = .); + + PROVIDE (__stack_end = .); + + PROVIDE (__heap_start = .); +} diff --git a/bertos/cpu/arm/scripts/at91sam7_512_rom.ld b/bertos/cpu/arm/scripts/at91sam7_512_rom.ld new file mode 100644 index 00000000..4826fc0d --- /dev/null +++ b/bertos/cpu/arm/scripts/at91sam7_512_rom.ld @@ -0,0 +1,143 @@ +/** + * \file + * + * + * \version $Id: sysirq_at91.c 18273 2007-10-11 14:53:02Z batt $ + * + * \author Daniele Basile + * + * \brief Script linker for Atmel AT91SAM7_512 family processors. + * + */ + + +ENTRY(_init) +SEARCH_DIR(.) +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* + * Define memory configuration for AT91SAM7_512 family + */ +MEMORY +{ + rom(rx) : org = 0x00100000, len = 512k + ram(rwx) : org = 0x00200000, len = 64k +} + + +/* + * Define stack size here + */ +FIQ_STACK_SIZE = 0x0100; +IRQ_STACK_SIZE = 0x0100; +ABT_STACK_SIZE = 0x0100; +UND_STACK_SIZE = 0x0100; +SVC_STACK_SIZE = 0x0400; + +/* + * Allocate section memory + */ +SECTIONS +{ + .text : + { + KEEP(*(.vectors)); + . = ALIGN (4); + KEEP(*(.init)); + . = ALIGN (4); + *(.rodata .rodata.*); + . = ALIGN (4); + *(.text .text.*); + . = ALIGN (4); + *(.glue_7t); + . = ALIGN(4); + *(.glue_7); + . = ALIGN(4); + } > rom + + _etext = .; + PROVIDE (__etext = .); + + .data : AT (_etext) + { + PROVIDE (__data_start = .); + *(.data .data.*) + . = ALIGN (4); + _edata = .; + PROVIDE (__data_end = .); + } > ram + + .bss : + { + PROVIDE (__bss_start = .); + *(.bss .bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + } > ram + + /* + * Allocated stack at the end of bss section. + * Data heap is allocate at end of stack. + */ + PROVIDE (__stack_start = .); + + PROVIDE (__stack_fiq_start = .); + . += FIQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_fiq_end = .); + + PROVIDE (__stack_irq_start = .); + . += IRQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_irq_end = .); + + PROVIDE (__stack_abt_start = .); + . += ABT_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_abt_end = .); + + PROVIDE (__stack_und_start = .); + . += UND_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_und_end = .); + + PROVIDE (__stack_svc_start = .); + . += SVC_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_svc_end = .); + + PROVIDE (__stack_end = .); + + PROVIDE (__heap_start = .); +} diff --git a/bertos/cpu/arm/scripts/at91sam7_64_ram.ld b/bertos/cpu/arm/scripts/at91sam7_64_ram.ld new file mode 100644 index 00000000..124edf79 --- /dev/null +++ b/bertos/cpu/arm/scripts/at91sam7_64_ram.ld @@ -0,0 +1,143 @@ +/** + * \file + * + * + * \version $Id: sysirq_at91.c 18273 2007-10-11 14:53:02Z batt $ + * + * \author Daniele Basile + * + * \brief Script linker for Atmel AT91SAM7_64 family processors. + * + */ + + +ENTRY(_init) +SEARCH_DIR(.) +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* + * Define memory configuration for AT91SAM7_64 family + */ +MEMORY +{ + rom(rx) : org = 0x00100000, len = 64k + ram(rwx) : org = 0x00200000, len = 16k +} + + +/* + * Define stack size here + */ +FIQ_STACK_SIZE = 0x0100; +IRQ_STACK_SIZE = 0x0100; +ABT_STACK_SIZE = 0x0100; +UND_STACK_SIZE = 0x0100; +SVC_STACK_SIZE = 0x0400; + +/* + * Allocate section memory + */ +SECTIONS +{ + .text : + { + KEEP(*(.vectors)); + . = ALIGN (4); + KEEP(*(.init)); + . = ALIGN (4); + *(.rodata .rodata.*); + . = ALIGN (4); + *(.text .text.*); + . = ALIGN (4); + *(.glue_7t); + . = ALIGN(4); + *(.glue_7); + . = ALIGN(4); + } > ram + + _etext = .; + PROVIDE (__etext = .); + + .data : AT (_etext) + { + PROVIDE (__data_start = .); + *(.data .data.*) + . = ALIGN (4); + _edata = .; + PROVIDE (__data_end = .); + } > ram + + .bss : + { + PROVIDE (__bss_start = .); + *(.bss .bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + } > ram + + /* + * Allocated stack at the end of bss section. + * Data heap is allocate at end of stack. + */ + PROVIDE (__stack_start = .); + + PROVIDE (__stack_fiq_start = .); + . += FIQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_fiq_end = .); + + PROVIDE (__stack_irq_start = .); + . += IRQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_irq_end = .); + + PROVIDE (__stack_abt_start = .); + . += ABT_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_abt_end = .); + + PROVIDE (__stack_und_start = .); + . += UND_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_und_end = .); + + PROVIDE (__stack_svc_start = .); + . += SVC_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_svc_end = .); + + PROVIDE (__stack_end = .); + + PROVIDE (__heap_start = .); +} diff --git a/bertos/cpu/arm/scripts/at91sam7_64_rom.ld b/bertos/cpu/arm/scripts/at91sam7_64_rom.ld new file mode 100644 index 00000000..93469d4e --- /dev/null +++ b/bertos/cpu/arm/scripts/at91sam7_64_rom.ld @@ -0,0 +1,143 @@ +/** + * \file + * + * + * \version $Id: sysirq_at91.c 18273 2007-10-11 14:53:02Z batt $ + * + * \author Daniele Basile + * + * \brief Script linker for Atmel AT91SAM7_64 family processors. + * + */ + + +ENTRY(_init) +SEARCH_DIR(.) +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* + * Define memory configuration for AT91SAM7_64 family + */ +MEMORY +{ + rom(rx) : org = 0x00100000, len = 64k + ram(rwx) : org = 0x00200000, len = 16k +} + + +/* + * Define stack size here + */ +FIQ_STACK_SIZE = 0x0100; +IRQ_STACK_SIZE = 0x0100; +ABT_STACK_SIZE = 0x0100; +UND_STACK_SIZE = 0x0100; +SVC_STACK_SIZE = 0x0400; + +/* + * Allocate section memory + */ +SECTIONS +{ + .text : + { + KEEP(*(.vectors)); + . = ALIGN (4); + KEEP(*(.init)); + . = ALIGN (4); + *(.rodata .rodata.*); + . = ALIGN (4); + *(.text .text.*); + . = ALIGN (4); + *(.glue_7t); + . = ALIGN(4); + *(.glue_7); + . = ALIGN(4); + } > rom + + _etext = .; + PROVIDE (__etext = .); + + .data : AT (_etext) + { + PROVIDE (__data_start = .); + *(.data .data.*) + . = ALIGN (4); + _edata = .; + PROVIDE (__data_end = .); + } > ram + + .bss : + { + PROVIDE (__bss_start = .); + *(.bss .bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + } > ram + + /* + * Allocated stack at the end of bss section. + * Data heap is allocate at end of stack. + */ + PROVIDE (__stack_start = .); + + PROVIDE (__stack_fiq_start = .); + . += FIQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_fiq_end = .); + + PROVIDE (__stack_irq_start = .); + . += IRQ_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_irq_end = .); + + PROVIDE (__stack_abt_start = .); + . += ABT_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_abt_end = .); + + PROVIDE (__stack_und_start = .); + . += UND_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_und_end = .); + + PROVIDE (__stack_svc_start = .); + . += SVC_STACK_SIZE; + . = ALIGN(4); + PROVIDE (__stack_svc_end = .); + + PROVIDE (__stack_end = .); + + PROVIDE (__heap_start = .); +} diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index c6a48b99..6c0d8f6e 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -51,6 +51,7 @@ #if defined(__ARM_AT91SAM7S64__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S64 1 #else #define CPU_ARM_AT91SAM7S64 0 @@ -58,6 +59,7 @@ #if defined(__ARM_AT91SAM7S128__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S128 1 #else #define CPU_ARM_AT91SAM7S128 0 @@ -65,14 +67,24 @@ #if defined(__ARM_AT91SAM7S256__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S256 1 #else #define CPU_ARM_AT91SAM7S256 0 #endif + #if defined(__ARM_AT91SAM7S512__) + #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 + #define CPU_ARM_AT91SAM7S512 1 + #else + #define CPU_ARM_AT91SAM7S512 0 + #endif + // AT91SAM7X core family #if defined(__ARM_AT91SAM7X128__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X128 1 #else #define CPU_ARM_AT91SAM7X128 0 @@ -80,11 +92,21 @@ #if defined(__ARM_AT91SAM7X256__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X256 1 #else #define CPU_ARM_AT91SAM7X256 0 #endif + + #if defined(__ARM_AT91SAM7X512__) + #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 + #define CPU_ARM_AT91SAM7X512 1 + #else + #define CPU_ARM_AT91SAM7X512 0 + #endif + #if defined (__ARM_LM3S1968__) #define CPU_ARM_LM3S 1 #define CPU_ARM_LM3S1968 1 @@ -92,12 +114,21 @@ #define CPU_ARM_LM3S1968 0 #endif + #if !defined(CPU_ARM_SAM7S_LARGE) + #define CPU_ARM_SAM7S_LARGE 0 + #endif + + #if !defined(CPU_ARM_SAM7X) + #define CPU_ARM_SAM7X 0 + #endif #if defined(CPU_ARM_AT91) #if CPU_ARM_AT91SAM7S32 + CPU_ARM_AT91SAM7S64 \ + CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 \ - + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 != 1 + + CPU_ARM_AT91SAM7S512 \ + + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 \ + + CPU_ARM_AT91SAM7X512 != 1 #error ARM CPU configuration error #endif #define CPU_ARM_LM3S 0 @@ -124,13 +155,19 @@ #define CPU_ARM_AT91 0 #define CPU_ARM_LM3S 0 + /* SAM7 sub-families */ + #define CPU_ARM_SAM7S_LARGE 0 + #define CPU_ARM_SAM7X 0 + /* ARM CPUs */ #define CPU_ARM_AT91SAM7S32 0 #define CPU_ARM_AT91SAM7S64 0 #define CPU_ARM_AT91SAM7S128 0 #define CPU_ARM_AT91SAM7S256 0 + #define CPU_ARM_AT91SAM7S512 0 #define CPU_ARM_AT91SAM7X128 0 #define CPU_ARM_AT91SAM7X256 0 + #define CPU_ARM_AT91SAM7X512 0 #define CPU_ARM_LM3S1968 0 #endif -- 2.25.1