From 3a9f71a83372f6e3d66ad64fd7ad5524940eec70 Mon Sep 17 00:00:00 2001 From: aleph Date: Tue, 19 Oct 2010 18:41:15 +0000 Subject: [PATCH] sam3n: fix confusion between interrupt numbers and peripheral ids. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4439 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/kdebug_sam3.c | 6 +-- bertos/cpu/cortex-m3/io/sam3.h | 62 +++++++++++----------- bertos/cpu/cortex-m3/io/sam3_ints.h | 71 ++++++++++++++++---------- 3 files changed, 80 insertions(+), 59 deletions(-) diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c index 80e5501f..9cfe143f 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c @@ -43,12 +43,12 @@ #if CONFIG_KDEBUG_PORT == 0 #define UART_BASE UART0_BASE - #define UART_INT INT_UART0 + #define UART_ID UART0_ID #define UART_PIO_BASE PIOA_BASE #define UART_PINS (BV(RXD0) | BV(TXD0)) #elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_AT91SAM3U) #define UART_BASE UART1_BASE - #define UART_INT INT_UART1 + #define UART_ID UART1_ID #define UART_PIO_BASE PIOB_BASE #define UART_PINS (BV(RXD1) | BV(TXD1)) #else @@ -78,7 +78,7 @@ INLINE void kdbg_hw_init(void) HWREG(UART_PIO_BASE + PIO_ABCDSR2_OFF) &= ~UART_PINS; /* Enable the peripheral clock */ - PMC_PCER |= BV(UART_INT); + PMC_PCER = BV(UART_ID); /* Reset and disable receiver & transmitter */ HWREG(UART_BASE + UART_CR_OFF) = BV(UART_CR_RSTRX) | BV(UART_CR_RSTTX) | BV(UART_CR_RXDIS) | BV(UART_CR_TXDIS); diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h index 2444f3ae..c637d59e 100644 --- a/bertos/cpu/cortex-m3/io/sam3.h +++ b/bertos/cpu/cortex-m3/io/sam3.h @@ -40,36 +40,40 @@ #include /* - * Peripherals IDs, same as interrupt numbers. + * Peripherals IDs. */ -#define SUPC_ID INT_SUPC ///< Supply Controller (SUPC) -#define RSTC_ID INT_RSTC ///< Reset Controller (RSTC) -#define RTC_ID INT_RTC ///< Real Time Clock (RTC) -#define RTT_ID INT_RTT ///< Real Time Timer (RTT) -#define WDT_ID INT_WDT ///< Watchdog Timer (WDT) -#define PMC_ID INT_PMC ///< Power Management Controller (PMC) -#define EFC_ID INT_EFC ///< Enhanced Flash Controller (EFC) -#define UART0_ID INT_UART0 ///< UART 0 (UART0) -#define UART1_ID INT_UART1 ///< UART 1 (UART1) -#define UART2_ID INT_UART2 ///< UART 0 (UART0) -#define UART3_ID INT_UART3 ///< UART 1 (UART1) -#define PIOA_ID INT_PIOA ///< Parallel I/O Controller A (PIOA) -#define PIOB_ID INT_PIOB ///< Parallel I/O Controller B (PIOB) -#define PIOC_ID INT_PIOC ///< Parallel I/O Controller C (PIOC) -#define US0_ID INT_USART0 ///< USART 0 (USART0) -#define US1_ID INT_USART1 ///< USART 1 (USART1) -#define TWI0_ID INT_TWI0 ///< Two Wire Interface 0 (TWI0) -#define TWI1_ID INT_TWI1 ///< Two Wire Interface 1 (TWI1) -#define SPI0_ID INT_SPI ///< Serial Peripheral Interface (SPI) -#define TC0_ID INT_TC0 ///< Timer/Counter 0 (TC0) -#define TC1_ID INT_TC1 ///< Timer/Counter 1 (TC1) -#define TC2_ID INT_TC2 ///< Timer/Counter 2 (TC2) -#define TC3_ID INT_TC3 ///< Timer/Counter 3 (TC3) -#define TC4_ID INT_TC4 ///< Timer/Counter 4 (TC4) -#define TC5_ID INT_TC5 ///< Timer/Counter 5 (TC5) -#define ADC_ID INT_ADC ///< Analog To Digital Converter (ADC) -#define DACC_ID INT_DACC ///< Digital To Analog Converter (DACC) -#define PWM_ID INT_PWM ///< Pulse Width Modulation (PWM) +/*\{*/ +#if CPU_CM3_AT91SAM3N + #define SUPC_ID 0 ///< Supply Controller (SUPC) + #define RSTC_ID 1 ///< Reset Controller (RSTC) + #define RTC_ID 2 ///< Real Time Clock (RTC) + #define RTT_ID 3 ///< Real Time Timer (RTT) + #define WDT_ID 4 ///< Watchdog Timer (WDT) + #define PMC_ID 5 ///< Power Management Controller (PMC) + #define EFC_ID 6 ///< Enhanced Flash Controller (EFC) + #define UART0_ID 8 ///< UART 0 (UART0) + #define UART1_ID 9 ///< UART 1 (UART1) + #define PIOA_ID 11 ///< Parallel I/O Controller A (PIOA) + #define PIOB_ID 12 ///< Parallel I/O Controller B (PIOB) + #define PIOC_ID 13 ///< Parallel I/O Controller C (PIOC) + #define US0_ID 14 ///< USART 0 (USART0) + #define US1_ID 15 ///< USART 1 (USART1) + #define TWI0_ID 19 ///< Two Wire Interface 0 (TWI0) + #define TWI1_ID 20 ///< Two Wire Interface 1 (TWI1) + #define SPI0_ID 21 ///< Serial Peripheral Interface (SPI) + #define TC0_ID 23 ///< Timer/Counter 0 (TC0) + #define TC1_ID 24 ///< Timer/Counter 1 (TC1) + #define TC2_ID 25 ///< Timer/Counter 2 (TC2) + #define TC3_ID 26 ///< Timer/Counter 3 (TC3) + #define TC4_ID 27 ///< Timer/Counter 4 (TC4) + #define TC5_ID 28 ///< Timer/Counter 5 (TC5) + #define ADC_ID 29 ///< Analog To Digital Converter (ADC) + #define DACC_ID 30 ///< Digital To Analog Converter (DACC) + #define PWM_ID 31 ///< Pulse Width Modulation (PWM) +#else + #error Peripheral IDs undefined +#endif +/*\}*/ /* * Hardware features for drivers. diff --git a/bertos/cpu/cortex-m3/io/sam3_ints.h b/bertos/cpu/cortex-m3/io/sam3_ints.h index 422ff511..88fc69f6 100644 --- a/bertos/cpu/cortex-m3/io/sam3_ints.h +++ b/bertos/cpu/cortex-m3/io/sam3_ints.h @@ -36,43 +36,60 @@ #ifndef SAM3_INTS_H #define SAM3_INTS_H +/** + * Defines for the fault assignments. + */ +/*\{*/ +#define FAULT_NMI 2 ///< NMI fault +#define FAULT_HARD 3 ///< Hard fault +#define FAULT_MPU 4 ///< MPU fault +#define FAULT_BUS 5 ///< Bus fault +#define FAULT_USAGE 6 ///< Usage fault +#define FAULT_SVCALL 11 ///< SVCall +#define FAULT_DEBUG 12 ///< Debug monitor +#define FAULT_PENDSV 14 ///< PendSV +#define FAULT_SYSTICK 15 ///< System Tick +/*\}*/ + /** * Defines for the interrupt assignments. */ /*\{*/ -#define INT_SUPC 0 ///< Supply Controller (SUPC) -#define INT_RSTC 1 ///< Reset Controller (RSTC) -#define INT_RTC 2 ///< Real Time Clock (RTC) -#define INT_RTT 3 ///< Real Time Timer (RTT) -#define INT_WDT 4 ///< Watchdog Timer (WDT) -#define INT_PMC 5 ///< Power Management Controller (PMC) -#define INT_EFC 6 ///< Enhanced Flash Controller (EFC) -#define INT_UART0 8 ///< UART 0 (UART0) -#define INT_UART1 9 ///< UART 1 (UART1) -#define INT_PIOA 11 ///< Parallel I/O Controller A (PIOA) -#define INT_PIOB 12 ///< Parallel I/O Controller B (PIOB) -#define INT_PIOC 13 ///< Parallel I/O Controller C (PIOC) -#define INT_USART0 14 ///< USART 0 (USART0) -#define INT_USART1 15 ///< USART 1 (USART1) -#define INT_TWI0 19 ///< Two Wire Interface 0 (TWI0) -#define INT_TWI1 20 ///< Two Wire Interface 1 (TWI1) -#define INT_SPI 21 ///< Serial Peripheral Interface (SPI) -#define INT_TC0 23 ///< Timer/Counter 0 (TC0) -#define INT_TC1 24 ///< Timer/Counter 1 (TC1) -#define INT_TC2 25 ///< Timer/Counter 2 (TC2) -#define INT_TC3 26 ///< Timer/Counter 3 (TC3) -#define INT_TC4 27 ///< Timer/Counter 4 (TC4) -#define INT_TC5 28 ///< Timer/Counter 5 (TC5) -#define INT_ADC 29 ///< Analog To Digital Converter (ADC) -#define INT_DACC 30 ///< Digital To Analog Converter (DACC) -#define INT_PWM 31 ///< Pulse Width Modulation (PWM) +#define INT_PERIPH_BASE 16 + +#define INT_SUPC (INT_PERIPH_BASE + SUPC_ID) ///< Supply Controller (SUPC) +#define INT_RSTC (INT_PERIPH_BASE + RSTC_ID) ///< Reset Controller (RSTC) +#define INT_RTC (INT_PERIPH_BASE + RTC_ID) ///< Real Time Clock (RTC) +#define INT_RTT (INT_PERIPH_BASE + RTT_ID) ///< Real Time Timer (RTT) +#define INT_WDT (INT_PERIPH_BASE + WDT_ID) ///< Watchdog Timer (WDT) +#define INT_PMC (INT_PERIPH_BASE + PMC_ID) ///< Power Management Controller (PMC) +#define INT_EFC (INT_PERIPH_BASE + EFC_ID) ///< Enhanced Flash Controller (EFC) +#define INT_UART0 (INT_PERIPH_BASE + UART0_ID) ///< UART 0 (UART0) +#define INT_UART1 (INT_PERIPH_BASE + UART1_ID) ///< UART 1 (UART1) +#define INT_PIOA (INT_PERIPH_BASE + PIOA_ID) ///< Parallel I/O Controller A (PIOA) +#define INT_PIOB (INT_PERIPH_BASE + PIOB_ID) ///< Parallel I/O Controller B (PIOB) +#define INT_PIOC (INT_PERIPH_BASE + PIOC_ID) ///< Parallel I/O Controller C (PIOC) +#define INT_US0 (INT_PERIPH_BASE + US0_ID) ///< USART 0 (USART0) +#define INT_US1 (INT_PERIPH_BASE + US1_ID) ///< USART 1 (USART1) +#define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID) ///< Two Wire Interface 0 (TWI0) +#define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID) ///< Two Wire Interface 1 (TWI1) +#define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID) ///< Serial Peripheral Interface (SPI) +#define INT_TC0 (INT_PERIPH_BASE + TC0_ID) ///< Timer/Counter 0 (TC0) +#define INT_TC1 (INT_PERIPH_BASE + TC1_ID) ///< Timer/Counter 1 (TC1) +#define INT_TC2 (INT_PERIPH_BASE + TC2_ID) ///< Timer/Counter 2 (TC2) +#define INT_TC3 (INT_PERIPH_BASE + TC3_ID) ///< Timer/Counter 3 (TC3) +#define INT_TC4 (INT_PERIPH_BASE + TC4_ID) ///< Timer/Counter 4 (TC4) +#define INT_TC5 (INT_PERIPH_BASE + TC5_ID) ///< Timer/Counter 5 (TC5) +#define INT_ADC (INT_PERIPH_BASE + ADC_ID) ///< Analog To Digital Converter (ADC) +#define INT_DACC (INT_PERIPH_BASE + DACC_ID) ///< Digital To Analog Converter (DACC) +#define INT_PWM (INT_PERIPH_BASE + PWM_ID) ///< Pulse Width Modulation (PWM) /*\}*/ /** * Total number of interrupts. */ /*\{*/ -#define NUM_INTERRUPTS 32 +#define NUM_INTERRUPTS 48 /*\}*/ #endif /* SAM3_INTS_H */ -- 2.25.1