From 452d25b78e551f18eb70bff8c9b764630cbc5161 Mon Sep 17 00:00:00 2001 From: arighi Date: Wed, 12 May 2010 15:01:50 +0000 Subject: [PATCH] STM32: correctly set PCLK1 to 36MHz (max allowed frequency). git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3669 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/clock_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c index 4b8cd898..c225da8d 100644 --- a/bertos/cpu/cortex-m3/drv/clock_stm32.c +++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c @@ -136,7 +136,7 @@ void clock_init(void) RCC->CFGR |= RCC_HCLK_DIV1 << 3; /* Configure system clock dividers: PCLK1 (36MHz) */ RCC->CFGR &= CFGR_PPRE1_RESET_MASK; - RCC->CFGR |= RCC_HCLK_DIV2 << 3; + RCC->CFGR |= RCC_HCLK_DIV2; /* Configure system clock dividers: HCLK */ RCC->CFGR &= CFGR_HPRE_RESET_MASK; RCC->CFGR |= RCC_SYSCLK_DIV1; -- 2.25.1