From 457ded51e2bb0fb6daec2fc4073a0b1fef4f48ae Mon Sep 17 00:00:00 2001 From: aleph Date: Thu, 2 Dec 2010 15:35:33 +0000 Subject: [PATCH] Add base support for STM32F101C4 Cortex-M3 cpu. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4608 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/attr.h | 2 +- bertos/cpu/cortex-m3/info/STM32F101C4.cdef | 68 +++++++++++++++++++ bertos/cpu/cortex-m3/io/stm32.h | 14 +++- .../cpu/cortex-m3/scripts/stm32f101c4_ram.ld | 49 +++++++++++++ .../cpu/cortex-m3/scripts/stm32f101c4_rom.ld | 49 +++++++++++++ bertos/cpu/detect.h | 11 ++- 6 files changed, 188 insertions(+), 5 deletions(-) create mode 100644 bertos/cpu/cortex-m3/info/STM32F101C4.cdef create mode 100644 bertos/cpu/cortex-m3/scripts/stm32f101c4_ram.ld create mode 100644 bertos/cpu/cortex-m3/scripts/stm32f101c4_rom.ld diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h index 2dab957f..8b1fa4c7 100644 --- a/bertos/cpu/attr.h +++ b/bertos/cpu/attr.h @@ -171,7 +171,7 @@ #define CPU_HARVARD 0 /// Valid pointers should be >= than this value (used for debug) - #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_SAM3) + #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3) #define CPU_RAM_START 0x20000000 #else #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000 diff --git a/bertos/cpu/cortex-m3/info/STM32F101C4.cdef b/bertos/cpu/cortex-m3/info/STM32F101C4.cdef new file mode 100644 index 00000000..334f36e2 --- /dev/null +++ b/bertos/cpu/cortex-m3/info/STM32F101C4.cdef @@ -0,0 +1,68 @@ +# +#-*- coding: utf-8 -*- +# +# \file +# +# +# General CPU info denfinition for Cortex-M3-based STM32F101C4 cpu. +# +# This file contain all info for the BeRTOS wizard. +# +# \author Stefano Fedrigo +# +# + +# Import the common settings for the path. +include("cm3.common") + +# CPU type used for flashing/debugging +MK_PROGRAMMER_CPU = "stm32" +MK_FLASH_SCRIPT = PRG_SCRIPTS_DIR + "arm/flash-stm32.sh" + +# CPU default clock frequency +CPU_DEFAULT_FREQ = "36000000UL" + +# Special CPU related tags. +CPU_TAGS += ["stm32"] + +# Additional hw drivers. +MK_CPU_CSRC += DRV_DIR + "gpio_stm32.c " + DRV_DIR + "clock_stm32.c " + +# Short description of the cpu. +CPU_DESC += [ "16 Kbytes on-chip flash memory", + "4 Kbytes on-chip SRAM memory", + "2 UARTs interfaces", + "1 I2C interface", + "1 ADC x10 channels 12-bit" ] + +# GCC flags for this cpu. +MK_CPU_CPPFLAGS += " -D__ARM_STM32F101C4__" +MK_CPU_LDFLAGS += " -T " + SCRIPT_DIR + "stm32f101c4_rom.ld" diff --git a/bertos/cpu/cortex-m3/io/stm32.h b/bertos/cpu/cortex-m3/io/stm32.h index 9c2fe1df..2db09213 100644 --- a/bertos/cpu/cortex-m3/io/stm32.h +++ b/bertos/cpu/cortex-m3/io/stm32.h @@ -51,7 +51,12 @@ #include "stm32_i2c.h" #include "stm32_flash.h" -#if CPU_CM3_STM32F103RB +#if CPU_CM3_STM32F101C4 + #define GPIO_USART1_TX_PIN BV(9) + #define GPIO_USART1_RX_PIN BV(10) + #define GPIO_USART2_TX_PIN BV(2) + #define GPIO_USART2_RX_PIN BV(3) +#elif CPU_CM3_STM32F103RB #define GPIO_USART1_TX_PIN BV(9) #define GPIO_USART1_RX_PIN BV(10) #define GPIO_USART2_TX_PIN BV(2) @@ -62,7 +67,10 @@ #error No USART pins are defined for select cpu #endif -#if CPU_CM3_STM32F103RB +#if CPU_CM3_STM32F101C4 + #define GPIO_I2C1_SCL_PIN BV(6) + #define GPIO_I2C1_SDA_PIN BV(7) +#elif CPU_CM3_STM32F103RB #define GPIO_I2C1_SCL_PIN BV(6) #define GPIO_I2C1_SDA_PIN BV(7) #define GPIO_I2C2_SCL_PIN BV(10) @@ -71,7 +79,7 @@ #error No i2c pins are defined for select cpu #endif -#if CPU_CM3_STM32F103RB +#if CPU_CM3_STM32F101C4 || CPU_CM3_STM32F103RB #define FLASH_PAGE_SIZE 1024 #else #error No embedded definition for select cpu diff --git a/bertos/cpu/cortex-m3/scripts/stm32f101c4_ram.ld b/bertos/cpu/cortex-m3/scripts/stm32f101c4_ram.ld new file mode 100644 index 00000000..0637501c --- /dev/null +++ b/bertos/cpu/cortex-m3/scripts/stm32f101c4_ram.ld @@ -0,0 +1,49 @@ +/** + * \file + * + * + * \author Stefano Fedrigo + * + * \brief Script for STM32F101C4 cpu. + * + */ + +/* + * Define memory configuration for STM32F101C4 + */ +MEMORY +{ + rom(rx) : org = 0x00000000, len = 16k + ram(rwx) : org = 0x20000000, len = 4k +} + +INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_ram.ld" + diff --git a/bertos/cpu/cortex-m3/scripts/stm32f101c4_rom.ld b/bertos/cpu/cortex-m3/scripts/stm32f101c4_rom.ld new file mode 100644 index 00000000..f2ea131c --- /dev/null +++ b/bertos/cpu/cortex-m3/scripts/stm32f101c4_rom.ld @@ -0,0 +1,49 @@ +/** + * \file + * + * + * \author Stefano Fedrigo + * + * \brief Script for STM32F101C4 cpu. + * + */ + +/* + * Define memory configuration for STM32F101C4 + */ +MEMORY +{ + rom(rx) : org = 0x00000000, len = 16k + ram(rwx) : org = 0x20000000, len = 4k +} + +INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_rom.ld" + diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index 7b57ae70..ce462b2e 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -205,6 +205,14 @@ #define CPU_CM3_LM3S8962 0 #endif + #if defined (__ARM_STM32F101C4__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F101C4 1 + #define CPU_NAME "STM32F101C4" + #else + #define CPU_CM3_STM32F101C4 0 + #endif + #if defined (__ARM_STM32F103RB__) #define CPU_CM3_STM32 1 #define CPU_CM3_STM32F103RB 1 @@ -258,7 +266,7 @@ #define CPU_CM3_STM32 0 #define CPU_CM3_SAM3 0 #elif defined (CPU_CM3_STM32) - #if CPU_CM3_STM32F103RB + 0 != 1 + #if CPU_CM3_STM32F101C4 + CPU_CM3_STM32F103RB + 0 != 1 #error STM32 Cortex-M3 CPU configuration error #endif #define CPU_CM3_LM3S 0 @@ -292,6 +300,7 @@ #define CPU_CM3_STM32 0 #define CPU_CM3_STM32F103RB 0 + #define CPU_CM3_STM32F101C4 0 #define CPU_CM3_SAM3 0 #define CPU_CM3_SAM3N 0 -- 2.25.1