From 47f6041abb0ab530496e5b9f3da08874f7ffa51c Mon Sep 17 00:00:00 2001 From: asterix Date: Tue, 12 Jul 2011 10:25:05 +0000 Subject: [PATCH] Fix the macro alignment bug. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4964 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/io/sam3_pmc.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h index 7c02328f..555d66c0 100644 --- a/bertos/cpu/cortex-m3/io/sam3_pmc.h +++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h @@ -126,16 +126,16 @@ #define PMC_PCER0 (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF))) ///< Peripheral Clock Enable Register #define PMC_PCDR0 (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF))) ///< Peripheral Clock Disable Register #define PMC_PCSR0 (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF))) ///< Peripheral Clock Status Register - #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR _OFF))) ///< UTMI clock register + #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR_OFF))) ///< UTMI clock register #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF))) ///< PLL Register #define PMC_USB_O (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF))) ///< USB clock register - #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0 _OFF))) ///< Programmable Clock 0 Register - #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1 _OFF))) ///< Programmable Clock 1 Register - #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2 _OFF))) ///< Programmable Clock 2 Register + #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0_OFF))) ///< Programmable Clock 0 Register + #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1_OFF))) ///< Programmable Clock 1 Register + #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2_OFF))) ///< Programmable Clock 2 Register #define PMC_PCER1 (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF))) ///< Peripheral Clock Enable Register #define PMC_PCDR1 (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF))) ///< Peripheral Clock Disable Register #define PMC_PCSR1 (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF))) ///< Peripheral Clock Status Register - #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR _OFF))) ///< Oscillator Calibration Register + #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR_OFF))) ///< Oscillator Calibration Register #define CKGR_PLLR CKGR_PLLAR #endif -- 2.25.1