From 63c71456afab075b78c0b0b5ddf932ef7d7b9a8b Mon Sep 17 00:00:00 2001 From: lottaviano Date: Fri, 5 Aug 2011 09:54:58 +0000 Subject: [PATCH] Fix various SAM3X register definitions and reformat. git-svn-id: https://src.develer.com/svnoss/bertos/branches/2.7@4995 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/io/sam3_pmc.h | 49 +++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h index 7c02328f..5bac08a7 100644 --- a/bertos/cpu/cortex-m3/io/sam3_pmc.h +++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h @@ -95,6 +95,25 @@ #endif /*\}*/ + +/** + * Programmable clock ids. + * \{ + */ +#define PMC_PCK0_ID 8 +#define PMC_PCK1_ID 9 +#define PMC_PCK2_ID 10 +/*\}*/ + +/** + * Programmable clock status. + * \{ + */ +#define PMC_PCKRDY0 8 ///< Programmable clock 0 ready. +#define PMC_PCKRDY1 9 ///< Programmable clock 1 ready. +#define PMC_PCKRDY2 10 ///< Programmable clock 2 ready. +/*\}*/ + /** * PMC registers. */ @@ -126,16 +145,16 @@ #define PMC_PCER0 (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF))) ///< Peripheral Clock Enable Register #define PMC_PCDR0 (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF))) ///< Peripheral Clock Disable Register #define PMC_PCSR0 (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF))) ///< Peripheral Clock Status Register - #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR _OFF))) ///< UTMI clock register + #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR_OFF))) ///< UTMI clock register #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF))) ///< PLL Register #define PMC_USB_O (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF))) ///< USB clock register - #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0 _OFF))) ///< Programmable Clock 0 Register - #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1 _OFF))) ///< Programmable Clock 1 Register - #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2 _OFF))) ///< Programmable Clock 2 Register + #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0_OFF))) ///< Programmable Clock 0 Register + #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1_OFF))) ///< Programmable Clock 1 Register + #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2_OFF))) ///< Programmable Clock 2 Register #define PMC_PCER1 (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF))) ///< Peripheral Clock Enable Register #define PMC_PCDR1 (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF))) ///< Peripheral Clock Disable Register #define PMC_PCSR1 (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF))) ///< Peripheral Clock Status Register - #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR _OFF))) ///< Oscillator Calibration Register + #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR_OFF))) ///< Oscillator Calibration Register #define CKGR_PLLR CKGR_PLLAR #endif @@ -231,9 +250,9 @@ INLINE void pmc_periphDisable(unsigned id) #define CKGR_MOR_MOSCRCF_SHIFT 4 #define CKGR_MOR_MOSCRCF_MASK (0x7 << CKGR_MOR_MOSCRCF_SHIFT) ///< Main On-Chip RC Oscillator Frequency Selection #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT))) -#define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_SHIFT) #define CKGR_MOR_MOSCXTST_SHIFT 8 #define CKGR_MOR_MOSCXTST_MASK (0xff << CKGR_MOR_MOSCXTST_SHIFT) ///< Main Crystal Oscillator Start-up Time #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT))) @@ -271,12 +290,12 @@ INLINE void pmc_periphDisable(unsigned id) * Defines for bit fields in PMC_MCKR register. */ /*\{*/ -#define PMC_MCKR_CSS_MASK 0x3 ///< Master Clock Source Selection mask +#define PMC_MCKR_CSS_MASK 0x3 ///< Master Clock Source Selection mask #define PMC_MCKR_CSS_SLOW_CLK 0x0 ///< Slow Clock is selected #define PMC_MCKR_CSS_MAIN_CLK 0x1 ///< Main Clock is selected #define PMC_MCKR_CSS_PLL_CLK 0x2 ///< PLL Clock is selected -#define PMC_MCKR_PRES_SHIFT 4 -#define PMC_MCKR_PRES_MASK (0x7 << PMC_MCKR_PRES_SHIFT) ///< Processor Clock Prescaler mask +#define PMC_MCKR_PRES_SHIFT 4 +#define PMC_MCKR_PRES_MASK (0x7 << PMC_MCKR_PRES_SHIFT) ///< Processor Clock Prescaler mask #define PMC_MCKR_PRES_CLK (0x0 << PMC_MCKR_PRES_SHIFT) ///< Selected clock #define PMC_MCKR_PRES_CLK_2 (0x1 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 2 #define PMC_MCKR_PRES_CLK_4 (0x2 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 4 @@ -285,20 +304,20 @@ INLINE void pmc_periphDisable(unsigned id) #define PMC_MCKR_PRES_CLK_32 (0x5 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 32 #define PMC_MCKR_PRES_CLK_64 (0x6 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 64 #define PMC_MCKR_PRES_CLK_3 (0x7 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 3 -#define PMC_MCKR_PLLDIV2 12 ///< PLL Divisor by 2 +#define PMC_MCKR_PLLDIV2 12 ///< PLL Divisor by 2 /*\}*/ /** * Defines for bit fields in PMC_PCK[3] register. */ /*\{*/ -#define PMC_PCK_CSS_MASK 0x7 ///< Master Clock Source Selection mask +#define PMC_PCK_CSS_MASK 0x7 ///< Master Clock Source Selection mask #define PMC_PCK_CSS_SLOW 0x0 ///< Slow Clock is selected #define PMC_PCK_CSS_MAIN 0x1 ///< Main Clock is selected #define PMC_PCK_CSS_PLL 0x2 ///< PLL Clock is selected #define PMC_PCK_CSS_MCK 0x4 ///< Master Clock is selected -#define PMC_PCK_PRES_SHIFT 4 -#define PMC_PCK_PRES_MASK (0x7 << PMC_PCK_PRES_SHIFT) ///< Programmable Clock Prescaler +#define PMC_PCK_PRES_SHIFT 4 +#define PMC_PCK_PRES_MASK (0x7 << PMC_PCK_PRES_SHIFT) ///< Programmable Clock Prescaler #define PMC_PCK_PRES_CLK (0x0 << PMC_PCK_PRES_SHIFT) ///< Selected clock #define PMC_PCK_PRES_CLK_2 (0x1 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 2 #define PMC_PCK_PRES_CLK_4 (0x2 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 4 -- 2.25.1