From 9a332b1eebc9dba4b9cc5cfa901fe414824ceea1 Mon Sep 17 00:00:00 2001 From: arighi Date: Tue, 13 Apr 2010 13:13:34 +0000 Subject: [PATCH] CM3: generic IRQ management module. Define an IRQ management module generic for all the Cortex-M3 family processors. Moreover, automatically set the appropriate priority and enable the IRQ when registering an ISR via sysirq_setHandler(). git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3423 38d2e660-2303-0410-9eaa-f027e97ec537 --- .../cortex-m3/drv/{irq_lm3s.c => irq_cm3.c} | 52 +++++++++++-------- .../cortex-m3/drv/{irq_lm3s.h => irq_cm3.h} | 9 +++- bertos/cpu/cortex-m3/drv/timer_lm3s.c | 2 +- bertos/cpu/cortex-m3/hw/init_lm3s.c | 2 +- examples/lm3s1968/lm3s1968.mk | 2 +- 5 files changed, 42 insertions(+), 25 deletions(-) rename bertos/cpu/cortex-m3/drv/{irq_lm3s.c => irq_cm3.c} (77%) rename bertos/cpu/cortex-m3/drv/{irq_lm3s.h => irq_cm3.h} (91%) diff --git a/bertos/cpu/cortex-m3/drv/irq_lm3s.c b/bertos/cpu/cortex-m3/drv/irq_cm3.c similarity index 77% rename from bertos/cpu/cortex-m3/drv/irq_lm3s.c rename to bertos/cpu/cortex-m3/drv/irq_cm3.c index 98112cad..a21439a7 100644 --- a/bertos/cpu/cortex-m3/drv/irq_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/irq_cm3.c @@ -38,12 +38,24 @@ #include /* ASSERT() */ #include /* LOG_ERR() */ #include -#include -#include "irq_lm3s.h" +#include "irq_cm3.h" static void (*irq_table[NUM_INTERRUPTS])(void) __attribute__((section("vtable"))); +/* Priority register / IRQ number table */ +static const uint32_t nvic_prio_reg[] = +{ + /* System exception registers */ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, + + /* External interrupts registers */ + NVIC_PRI0, NVIC_PRI1, NVIC_PRI2, NVIC_PRI3, + NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, + NVIC_PRI12, NVIC_PRI13 +}; + /* Unhandled IRQ */ static NAKED NORETURN void unhandled_isr(void) { @@ -58,25 +70,22 @@ static NAKED NORETURN void unhandled_isr(void) void sysirq_setPriority(sysirq_t irq, int prio) { uint32_t pos = (irq & 3) * 8; - reg32_t reg; - - switch (irq >> 2) - { - case 1: - reg = NVIC_SYS_PRI1; - break; - case 2: - reg = NVIC_SYS_PRI2; - break; - case 3: - reg = NVIC_SYS_PRI3; - break; - default: - ASSERT(0); - return; - } - HWREG(reg) &= ~(0xff << pos); - HWREG(reg) |= prio << pos; + reg32_t reg = nvic_prio_reg[irq >> 2]; + uint32_t val; + + val = HWREG(reg); + val &= ~(0xff << pos); + val |= prio << pos; + HWREG(reg) = val; +} + +static void sysirq_enable(sysirq_t irq) +{ + /* Enable the IRQ line (only for generic IRQs) */ + if (irq >= 16 && irq < 48) + HWREG(NVIC_EN0) = 1 << (irq - 16); + else if (irq >= 48) + HWREG(NVIC_EN1) = 1 << (irq - 48); } void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler) @@ -88,6 +97,7 @@ void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler) IRQ_SAVE_DISABLE(flags); irq_table[irq] = handler; sysirq_setPriority(irq, IRQ_PRIO); + sysirq_enable(irq); IRQ_RESTORE(flags); } diff --git a/bertos/cpu/cortex-m3/drv/irq_lm3s.h b/bertos/cpu/cortex-m3/drv/irq_cm3.h similarity index 91% rename from bertos/cpu/cortex-m3/drv/irq_lm3s.h rename to bertos/cpu/cortex-m3/drv/irq_cm3.h index 8913183d..a3f2ded4 100644 --- a/bertos/cpu/cortex-m3/drv/irq_lm3s.h +++ b/bertos/cpu/cortex-m3/drv/irq_cm3.h @@ -30,7 +30,7 @@ * * --> * - * \brief IRQ management for the Cortex M3 processor. + * \brief IRQ management for the Cortex-M3 processor. * * \author Andrea Righi */ @@ -38,6 +38,13 @@ #ifndef DRV_CORTEX_M3_SYSIRQ_H #define DRV_CORTEX_M3_SYSIRQ_H +#if CPU_CM3_LM3S + #include +/*#elif Add other families here */ +#else + #error Unknown CPU +#endif + typedef void (*sysirq_handler_t)(void); typedef unsigned int sysirq_t; diff --git a/bertos/cpu/cortex-m3/drv/timer_lm3s.c b/bertos/cpu/cortex-m3/drv/timer_lm3s.c index 096bff92..49b9fa8e 100644 --- a/bertos/cpu/cortex-m3/drv/timer_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/timer_lm3s.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include "timer_lm3s.h" INLINE void timer_hw_setPeriod(unsigned long period) diff --git a/bertos/cpu/cortex-m3/hw/init_lm3s.c b/bertos/cpu/cortex-m3/hw/init_lm3s.c index caac9d09..0c0a05b7 100644 --- a/bertos/cpu/cortex-m3/hw/init_lm3s.c +++ b/bertos/cpu/cortex-m3/hw/init_lm3s.c @@ -42,7 +42,7 @@ #include /* PAUSE */ #include /* IRQ_DISABLE */ #include -#include +#include #include #include #include "switch_ctx_cm3.h" diff --git a/examples/lm3s1968/lm3s1968.mk b/examples/lm3s1968/lm3s1968.mk index dbbea22b..e90b31d1 100644 --- a/examples/lm3s1968/lm3s1968.mk +++ b/examples/lm3s1968/lm3s1968.mk @@ -41,11 +41,11 @@ lm3s1968_CSRC = \ bertos/kern/preempt.c \ bertos/kern/signal.c \ bertos/cpu/cortex-m3/drv/gpio_lm3s.c \ - bertos/cpu/cortex-m3/drv/irq_lm3s.c \ bertos/cpu/cortex-m3/drv/timer_lm3s.c \ bertos/cpu/cortex-m3/drv/clock_lm3s.c \ bertos/cpu/cortex-m3/drv/kdebug_lm3s.c \ bertos/cpu/cortex-m3/drv/ssi_lm3s.c \ + bertos/cpu/cortex-m3/drv/irq_cm3.c \ bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c \ bertos/cpu/cortex-m3/hw/init_lm3s.c -- 2.25.1