From ac85598df47d68e71ce45b9b0803b1d885c11084 Mon Sep 17 00:00:00 2001 From: arighi Date: Fri, 8 Apr 2011 09:44:54 +0000 Subject: [PATCH] CM3: add support to the IAR Embedded Workbench(TM) compiler Allow to build BeRTOS projects based on the CM3 architecture with the IAR compiler. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4837 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/irq_cm3.c | 10 +++++ bertos/cpu/cortex-m3/drv/kdebug_sam3.c | 2 + bertos/cpu/cortex-m3/hw/crt_cm3_iar.S | 47 +++++++++++++++++++++++ bertos/cpu/cortex-m3/hw/iar_cm3.S | 28 ++++++++++++++ bertos/cpu/cortex-m3/hw/init_cm3.c | 2 + bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c | 3 ++ bertos/cpu/cortex-m3/hw/vectors_cm3_iar.S | 27 +++++++++++++ 7 files changed, 119 insertions(+) create mode 100644 bertos/cpu/cortex-m3/hw/crt_cm3_iar.S create mode 100644 bertos/cpu/cortex-m3/hw/iar_cm3.S create mode 100644 bertos/cpu/cortex-m3/hw/vectors_cm3_iar.S diff --git a/bertos/cpu/cortex-m3/drv/irq_cm3.c b/bertos/cpu/cortex-m3/drv/irq_cm3.c index bbae8324..14311d95 100644 --- a/bertos/cpu/cortex-m3/drv/irq_cm3.c +++ b/bertos/cpu/cortex-m3/drv/irq_cm3.c @@ -41,8 +41,14 @@ #include /* LOG_ERR() */ #include + +#ifdef __IAR_SYSTEMS_ICC__ +#pragma data_alignment=0x400 +static void (*irq_table[NUM_INTERRUPTS])(void); +#else static void (*irq_table[NUM_INTERRUPTS])(void) __attribute__((section("vtable"))); +#endif /* Priority register / IRQ number table */ static const uint32_t nvic_prio_reg[] = @@ -62,7 +68,11 @@ static NAKED NORETURN void unhandled_isr(void) { register uint32_t reg; +#ifdef __IAR_SYSTEMS_ICC__ + reg = CPU_READ_IPSR(); +#else asm volatile ("mrs %0, ipsr" : "=r"(reg)); +#endif LOG_ERR("unhandled IRQ %lu\n", reg); while (1) PAUSE; diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c index 5297d602..45b2cf59 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c @@ -38,6 +38,8 @@ #include #include /* for BV() */ +#include + #include diff --git a/bertos/cpu/cortex-m3/hw/crt_cm3_iar.S b/bertos/cpu/cortex-m3/hw/crt_cm3_iar.S new file mode 100644 index 00000000..6bb71e1f --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/crt_cm3_iar.S @@ -0,0 +1,47 @@ + MODULE ?cstartup + +CONTROL_UNPRIVILEGED SET 1 +CONTROL_PSP SET 2 + + AAPCS INTERWORK, VFP_COMPATIBLE, ROPI + PRESERVE8 + + SECTION .vtable:CODE:NOROOT(3) + + RSEG IRQ_STACK:DATA(3) + RSEG CSTACK:DATA(3) + RSEG DATABSS:DATA(3) + + EXTERN __cmain + EXTERN __init2 + EXTERN __region_RAM_end__ + PUBLIC __iar_program_start + + SECTION .text:CODE:REORDER(2) + + PUBWEAK __dummy_init + __dummy_init: + bx lr + + THUMB + __iar_program_start: + cpsid i + ldr r0, =__region_RAM_end__ + sub r0, r0, #16 + msr psp, r0 + + movs r0, #CONTROL_PSP + msr control, r0 + isb + + bl __init2 + + cpsie i + mov r0, #0 + mov r1, #0 + bl __cmain + end: + wfi + b end + + END diff --git a/bertos/cpu/cortex-m3/hw/iar_cm3.S b/bertos/cpu/cortex-m3/hw/iar_cm3.S new file mode 100644 index 00000000..c537384d --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/iar_cm3.S @@ -0,0 +1,28 @@ + SECTION .text:CODE(2) + + ; Exported functions + EXPORT CPU_READ_IPSR + EXPORT irq_running + EXPORT asm_switch_context + + CPU_READ_IPSR: + mrs r0, ipsr + bx lr + + irq_running: + mrs r0, msp + cmp sp, r0 + ite ne + movne r0, #0x0 + moveq r0, #0x1 + bx lr + + asm_switch_context: + mrs r12, psp + stmdb r12!, {r4-r11, lr} + str r12, [r1] + ldr r12, [r0] + ldmia r12!, {r4-r11, lr} + msr psp, r12 + bx lr + END diff --git a/bertos/cpu/cortex-m3/hw/init_cm3.c b/bertos/cpu/cortex-m3/hw/init_cm3.c index b67900fc..4ce2f86f 100644 --- a/bertos/cpu/cortex-m3/hw/init_cm3.c +++ b/bertos/cpu/cortex-m3/hw/init_cm3.c @@ -52,7 +52,9 @@ #include +#ifndef __IAR_SYSTEMS_ICC__ extern size_t __text_end, __data_start, __data_end, __bss_start, __bss_end; +#endif extern void __init2(void); diff --git a/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c b/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c index 7b36d902..b9afaae0 100644 --- a/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c +++ b/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.c @@ -123,6 +123,8 @@ void NAKED pendsv_handler(void) : "memory"); } #else /* !CONFIG_KERN_PREEMPT */ +#ifdef __IAR_SYSTEMS_ICC__ +#else /* __IAR_SYSTEMS_ICC__ */ void NAKED asm_switch_context(cpu_stack_t **new_sp, cpu_stack_t **old_sp) { register cpu_stack_t **_new_sp asm("r0") = new_sp; @@ -142,4 +144,5 @@ void NAKED asm_switch_context(cpu_stack_t **new_sp, cpu_stack_t **old_sp) "bx lr" : : "r"(_new_sp), "r"(_old_sp) : "ip", "memory"); } +#endif /* __IAR_SYSTEMS_ICC__ */ #endif /* CONFIG_KERN_PREEMPT */ diff --git a/bertos/cpu/cortex-m3/hw/vectors_cm3_iar.S b/bertos/cpu/cortex-m3/hw/vectors_cm3_iar.S new file mode 100644 index 00000000..eab02c68 --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/vectors_cm3_iar.S @@ -0,0 +1,27 @@ + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .vtable:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD default_isr + DCD default_isr + + SECTION .text:CODE:REORDER(1) + THUMB + +default_isr: + wfi + b default_isr + + END -- 2.25.1