From bb26872e115380a4354346bce26a0e1ec94f7628 Mon Sep 17 00:00:00 2001 From: lottaviano Date: Fri, 3 Jul 2009 14:20:05 +0000 Subject: [PATCH] Import SPI with DMA driver. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@2735 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cfg/cfg_spi_dma.h | 68 ++++++++ bertos/cpu/arm/drv/spi_dma_at91.c | 251 ++++++++++++++++++++++++++++++ bertos/cpu/arm/drv/spi_dma_at91.h | 73 +++++++++ bertos/cpu/arm/io/at91_spi.h | 20 +-- bertos/hw/hw_spi_dma.h | 48 ++++++ 5 files changed, 450 insertions(+), 10 deletions(-) create mode 100644 bertos/cfg/cfg_spi_dma.h create mode 100644 bertos/cpu/arm/drv/spi_dma_at91.c create mode 100644 bertos/cpu/arm/drv/spi_dma_at91.h create mode 100644 bertos/hw/hw_spi_dma.h diff --git a/bertos/cfg/cfg_spi_dma.h b/bertos/cfg/cfg_spi_dma.h new file mode 100644 index 00000000..0a69f757 --- /dev/null +++ b/bertos/cfg/cfg_spi_dma.h @@ -0,0 +1,68 @@ +/** + * \file + * + * + * \brief Configuration file for spi dma module. + * + * \version $Id$ + * + * \author Francesco Sacchi + */ + +#ifndef CFG_SPI_DMA_H +#define CFG_SPI_DMA_H + +/** + * Size of the outbound FIFO buffer for SPI DMA [bytes]. + * $WIZ$ type = "int" + * $WIZ$ min = 2 + */ +#define CONFIG_SPI_DMA_TXBUFSIZE 512 + + +/** + * Max size received for each DMA transfer [bytes]. + * Longer buffers will be split in two or more transfers of this size. + * $WIZ$ type = "int" + * $WIZ$ min = 1 + */ +#define CONFIG_SPI_DMA_MAX_RX 512 + + +/** + * Default transmit timeout (ms). Set to -1 to disable timeout support. + * $WIZ$ type = "int" + * $WIZ$ min = -1 + */ +#define CONFIG_SPI_DMA_TX_TIMEOUT -1 + + +#endif /* CFG_SER_H */ diff --git a/bertos/cpu/arm/drv/spi_dma_at91.c b/bertos/cpu/arm/drv/spi_dma_at91.c new file mode 100644 index 00000000..406e9d87 --- /dev/null +++ b/bertos/cpu/arm/drv/spi_dma_at91.c @@ -0,0 +1,251 @@ +/** + * \file + * + * + * \brief SPI driver with DMA. + * + * \version $Id$ + * \author Francesco Sacchi + * \author Luca Ottaviano + */ + +#include "cfg/cfg_spi_dma.h" + +#include "spi_dma_at91.h" +#include "hw/hw_spi_dma.h" + +#include +#include +#include +#include + +#include +#include + +#include /* memset */ + +static uint8_t tx_fifo_buffer[CONFIG_SPI_DMA_TXBUFSIZE]; +static FIFOBuffer tx_fifo; +static KFileFifo kfifo; + + +INLINE void spi_dma_startTx(void) +{ + if (fifo_isempty(&tx_fifo)) + return; + + if (SPI0_SR & BV(SPI_TXBUFE)) + { + SPI0_PTCR = BV(PDC_TXTDIS); + SPI0_TPR = (reg32_t)tx_fifo.head; + if (tx_fifo.head < tx_fifo.tail) + SPI0_TCR = tx_fifo.tail - tx_fifo.head; + else + SPI0_TCR = tx_fifo.end - tx_fifo.head + 1; + + SPI0_PTCR = BV(PDC_TXTEN); + } +} + +static void spi0_dma_write_irq_handler(void) __attribute__ ((interrupt)); +static void spi0_dma_write_irq_handler(void) +{ + SPI_DMA_STROBE_ON(); + /* Pop sent chars from FIFO */ + tx_fifo.head = (uint8_t *)SPI0_TPR; + if (tx_fifo.head > tx_fifo.end) + tx_fifo.head = tx_fifo.begin; + + spi_dma_startTx(); + + AIC_EOICR = 0; + SPI_DMA_STROBE_OFF(); +} + + +void spi_dma_setclock(uint32_t rate) +{ + SPI0_CSR0 &= ~SPI_SCBR; + + ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate)); + SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT; +} + +static size_t spi_dma_write(UNUSED_ARG(struct KFile *, fd), const void *_buf, size_t size) +{ + size_t count, total_wr = 0; + const uint8_t *buf = (const uint8_t *) _buf; + + // copy buffer to internal fifo + while (size) + { + #if CONFIG_SPI_DMA_TX_TIMEOUT != -1 + ticks_t start = timer_clock(); + while (fifo_isfull(&tx_fifo) && (timer_clock() - start < ms_to_ticks(CONFIG_SPI_DMA_TX_TIMEOUT))) + cpu_relax(); + + if (fifo_isfull(&tx_fifo)) + break; + #else + while (fifo_isfull(&tx_fifo)) + cpu_relax(); + #endif /* CONFIG_SPI_DMA_TX_TIMEOUT */ + + // FIXME: improve copy performance + count = kfile_write(&kfifo.fd, buf, size); + size -= count; + buf += count; + total_wr += count; + spi_dma_startTx(); + } + + return total_wr; +} + +static int spi_dma_flush(UNUSED_ARG(struct KFile *, fd)) +{ + /* Wait FIFO flush */ + while (!fifo_isempty(&tx_fifo)) + cpu_relax(); + + /* Wait until last bit has been shifted out */ + while (!(SPI0_SR & BV(SPI_TXEMPTY))) + cpu_relax(); + + return 0; +} + +static void spi0_dma_read_irq_handler(void) __attribute__ ((interrupt)); +static void spi0_dma_read_irq_handler(void) +{ + /* do nothing */ + AIC_EOICR = 0; +} + +/* + * Dummy buffer used to transmit 0xff chars while receiving data. + * This buffer is completetly constant and the compiler should allocate it + * in flash memory. + */ +static const uint8_t tx_dummy_buf[CONFIG_SPI_DMA_MAX_RX] = { [0 ... (CONFIG_SPI_DMA_MAX_RX - 1)] = 0xFF }; + +static size_t spi_dma_read(struct KFile *fd, void *_buf, size_t size) +{ + size_t count, total_rx = 0; + uint8_t *buf = (uint8_t *)_buf; + + spi_dma_flush(fd); + + /* Dummy irq handler that do nothing */ + AIC_SVR(SPI0_ID) = spi0_dma_read_irq_handler; + + while (size) + { + count = MIN(size, (size_t)CONFIG_SPI_DMA_MAX_RX); + + SPI0_PTCR = BV(PDC_TXTDIS) | BV(PDC_RXTDIS); + + SPI0_RPR = (reg32_t)buf; + SPI0_RCR = count; + SPI0_TPR = (reg32_t)tx_dummy_buf; + SPI0_TCR = count; + + /* Avoid reading the previous sent char */ + *buf = SPI0_RDR; + + /* Start transfer */ + SPI0_PTCR = BV(PDC_RXTEN) | BV(PDC_TXTEN); + + /* wait for transfer to finish */ + while (!(SPI0_SR & BV(SPI_ENDRX))) + cpu_relax(); + + size -= count; + total_rx += count; + buf += count; + } + SPI0_PTCR = BV(PDC_RXTDIS) | BV(PDC_TXTDIS); + + /* set write irq handler back in place */ + AIC_SVR(SPI0_ID) = spi0_dma_write_irq_handler; + + return total_rx; +} + +#define SPI_DMA_IRQ_PRIORITY 4 + +void spi_dma_init(SpiDmaAt91 *spi) +{ + /* Disable PIO on SPI pins */ + PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); + + /* Reset device */ + SPI0_CR = BV(SPI_SWRST); + + /* + * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device, + * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0 + */ + SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); + + /* + * Set SPI mode. + * At reset clock division factor is set to 0, that is + * *forbidden*. Set SPI clock to minimum to keep it valid. + */ + SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT); + + /* Disable all irqs */ + SPI0_IDR = 0xFFFFFFFF; + /* Set the vector. */ + AIC_SVR(SPI0_ID) = spi0_dma_write_irq_handler; + /* Initialize to edge triggered with defined priority. */ + AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SPI_DMA_IRQ_PRIORITY; + /* Enable the USART IRQ */ + AIC_IECR = BV(SPI0_ID); + PMC_PCER = BV(SPI0_ID); + + /* Enable interrupt on tx buffer empty */ + SPI0_IER = BV(SPI_ENDTX); + + /* Enable SPI */ + SPI0_CR = BV(SPI_SPIEN); + + DB(spi->fd._type = KFT_SPIDMAAT91); + spi->fd.write = spi_dma_write; + spi->fd.read = spi_dma_read; + spi->fd.flush = spi_dma_flush; + + fifo_init(&tx_fifo, tx_fifo_buffer, sizeof(tx_fifo_buffer)); + kfilefifo_init(&kfifo, &tx_fifo); + + SPI_DMA_STROBE_INIT(); +} diff --git a/bertos/cpu/arm/drv/spi_dma_at91.h b/bertos/cpu/arm/drv/spi_dma_at91.h new file mode 100644 index 00000000..6ceef4aa --- /dev/null +++ b/bertos/cpu/arm/drv/spi_dma_at91.h @@ -0,0 +1,73 @@ +/** + * \file + * + * + * \brief SPI driver with DMA. + * + * \note Only one copy of SpiDmaAt91 is allowed for each application. + * + * \version $Id$ + * \author Francesco Sacchi + * \author Luca Ottaviano + */ + +#ifndef DRV_SPI_DMA_AT91_H +#define DRV_SPI_DMA_AT91_H + +#include + +typedef struct SpiDmaAt91 +{ + KFile fd; +} SpiDmaAt91; + +#define KFT_SPIDMAAT91 MAKE_ID('S', 'P', 'I', 'A') + +INLINE SpiDmaAt91 * SPIDMAAT91_CAST(KFile *fd) +{ + ASSERT(fd->_type == KFT_SPIDMAAT91); + return (SpiDmaAt91 *)fd; +} + +/** + * Init DMA SPI driver. + * \param spi A pointer to a SpiDmaAt91 structure. + */ +void spi_dma_init(SpiDmaAt91 *spi); + +/** + * Set the clock rate for SPI bus. + * + * \param rate The rate you want to set for SPI. + */ +void spi_dma_setclock(uint32_t rate); + +#endif /* DRV_SPI_DMA_AT91_H */ diff --git a/bertos/cpu/arm/io/at91_spi.h b/bertos/cpu/arm/io/at91_spi.h index 4766b75d..fd6bb746 100644 --- a/bertos/cpu/arm/io/at91_spi.h +++ b/bertos/cpu/arm/io/at91_spi.h @@ -233,16 +233,16 @@ #define SPI0_CSR2 (*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0. #define SPI0_CSR3 (*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0. #if defined(SPI_HAS_PDC) - #define SPI0_RPR (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF)) ///< PDC channel 0 receive pointer register. - #define SPI0_RCR (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF)) ///< PDC channel 0 receive counter register. - #define SPI0_TPR (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF)) ///< PDC channel 0 transmit pointer register. - #define SPI0_TCR (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF)) ///< PDC channel 0 transmit counter register. - #define SPI0_RNPR (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF)) ///< PDC channel 0 receive next pointer register. - #define SPI0_RNCR (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF)) ///< PDC channel 0 receive next counter register. - #define SPI0_TNPR (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF)) ///< PDC channel 0 transmit next pointer register. - #define SPI0_TNCR (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF)) ///< PDC channel 0 transmit next counter register. - #define SPI0_PTCR (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF)) ///< PDC channel 0 transfer control register. - #define SPI0_PTSR (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF)) ///< PDC channel 0 transfer status register. + #define SPI0_RPR (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))) ///< PDC channel 0 receive pointer register. + #define SPI0_RCR (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))) ///< PDC channel 0 receive counter register. + #define SPI0_TPR (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))) ///< PDC channel 0 transmit pointer register. + #define SPI0_TCR (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))) ///< PDC channel 0 transmit counter register. + #define SPI0_RNPR (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register. + #define SPI0_RNCR (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register. + #define SPI0_TNPR (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register. + #define SPI0_TNCR (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register. + #define SPI0_PTCR (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register. + #define SPI0_PTSR (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register. #endif /* SPI_HAS_PDC */ #endif /* SPI0_BASE */ /*\}*/ diff --git a/bertos/hw/hw_spi_dma.h b/bertos/hw/hw_spi_dma.h new file mode 100644 index 00000000..e0714d43 --- /dev/null +++ b/bertos/hw/hw_spi_dma.h @@ -0,0 +1,48 @@ +/** + * \file + * + * + * \brief SPI DMA driver hardware-specific definitions. + * + * \version $Id$ + * + * \author Francesco Sacchi + */ + +#ifndef HW_SPI_DMA_H +#define HW_SPI_DMA_H + +#define SPI_DMA_STROBE_INIT() do {/*PIOA_PER = BV(13); PIOA_OER = BV(13);*/} while(0) + +#define SPI_DMA_STROBE_ON() do {/*PIOA_CODR = BV(13);*/} while(0) +#define SPI_DMA_STROBE_OFF() do {/*PIOA_SODR = BV(13);*/} while(0) + +#endif /* HW_SPI_DMA_H */ -- 2.25.1