From bed65d274bdbfe916cf33a3b9ce480aa315fea18 Mon Sep 17 00:00:00 2001 From: asterix Date: Tue, 29 Mar 2011 09:59:20 +0000 Subject: [PATCH] Fix pasto. Add define for tc clock selections. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4818 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/io/sam3_tc.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/bertos/cpu/cortex-m3/io/sam3_tc.h b/bertos/cpu/cortex-m3/io/sam3_tc.h index d6212a17..a918f6c8 100644 --- a/bertos/cpu/cortex-m3/io/sam3_tc.h +++ b/bertos/cpu/cortex-m3/io/sam3_tc.h @@ -49,14 +49,14 @@ /** * Timer conter control register */ -#define TC0_CCR0_OFF 0x00 ///< TC0 Channel Control Register (channel = 0). +#define TC0_CCR0_OFF 0x00 ///< TC0 Channel Control Register (channel = 0). #define TC0_CCR0 (*((reg32_t*)(TC0_BASE + TC0_CCR0_OFF))) ///< TC0 Channel Control Register (channel = 0). -#define TC0_CMR0_OFF 0x04 ///< TC0 Channel Mode Register (channel = 0). -#define TC0_CMR0 (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF))) ///< TC0 Channel Mode Register (channel = 0). +#define TC0_CMR0_OFF 0x04 ///< TC0 Channel Mode Register (channel = 0). +#define TC0_CMR0 (*((reg32_t*)(TC0_BASE + TC0_CMR0_OFF))) ///< TC0 Channel Mode Register (channel = 0). -#define TC_CMR_CPCTRG 14 ///< RC Compare Trigger Enable -#define TC_CMR_WAVE 15 ///< Waveform mode is enabled +#define TC_CMR_CPCTRG 14 ///< RC Compare Trigger Enable +#define TC_CMR_WAVE 15 ///< Waveform mode is enabled #define TC_CMR_ACPA_SET 0x10000 ///< RA Compare Effect: set #define TC_CMR_ACPA_CLEAR 0x20000 ///< RA Compare Effect: clear @@ -66,13 +66,13 @@ #define TC_CMR_ACPC_CLEAR 0x80000 ///< RC Compare Effect: clear #define TC_CMR_ACPC_TOGGLE 0xC0000 ///< RC Compare Effect: toggle -#define TC_CCR_CLKEN 0 ///< Counter Clock Enable Command -#define TC_CCR_CLKDIS 1 ///< Counter Clock Disable Command -#define TC_CCR_SWTRG 2 ///< Software Trigger Command +#define TC_CCR_CLKEN 0 ///< Counter Clock Enable Command +#define TC_CCR_CLKDIS 1 ///< Counter Clock Disable Command +#define TC_CCR_SWTRG 2 ///< Software Trigger Command +#define TC_TIMER_CLOCK1 0 ///< Select timer clock TCLK1 - -#define TC0_SMMR0_OFF 0x08 ///< TC0 Stepper Motor Mode Register (channel = 0). +#define TC0_SMMR0_OFF 0x08 ///< TC0 Stepper Motor Mode Register (channel = 0). #define TC0_SMMR0 (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 0). #define TC0_CV0_OFF 0x10 ///< TC0 Conter Vale (channel = 0). -- 2.25.1