From c37e6a3f6900ec803c2608fb387054247bab88aa Mon Sep 17 00:00:00 2001 From: aleph Date: Wed, 27 Oct 2010 17:17:32 +0000 Subject: [PATCH] Change filename and macros from AT91SAM3.. to SAM3.. to conform to Atmel's official product naming. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4476 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/attr.h | 2 +- bertos/cpu/cortex-m3/drv/clock_cm3.h | 2 +- bertos/cpu/cortex-m3/drv/clock_sam3.c | 2 +- bertos/cpu/cortex-m3/drv/clock_sam3.h | 8 +- bertos/cpu/cortex-m3/drv/irq_cm3.h | 2 +- bertos/cpu/cortex-m3/drv/kdebug_cm3.c | 2 +- bertos/cpu/cortex-m3/drv/kdebug_sam3.c | 4 +- bertos/cpu/cortex-m3/drv/ser_cm3.h | 2 +- bertos/cpu/cortex-m3/drv/ser_sam3.c | 12 +-- bertos/cpu/cortex-m3/drv/ser_sam3.h | 2 +- bertos/cpu/cortex-m3/drv/timer_cm3.h | 2 +- .../info/{AT91SAM3N4.cdef => SAM3N4.cdef} | 4 +- bertos/cpu/cortex-m3/io/cm3.h | 2 +- bertos/cpu/cortex-m3/io/sam3.h | 6 +- bertos/cpu/cortex-m3/io/sam3_flash.h | 2 +- bertos/cpu/cortex-m3/io/sam3_ints.h | 2 +- bertos/cpu/cortex-m3/io/sam3_nvic.h | 2 +- bertos/cpu/cortex-m3/io/sam3_pio.h | 2 +- bertos/cpu/cortex-m3/io/sam3_pmc.h | 2 +- bertos/cpu/cortex-m3/io/sam3_spi.h | 2 +- bertos/cpu/cortex-m3/io/sam3_sysctl.h | 2 +- bertos/cpu/cortex-m3/io/sam3_uart.h | 4 +- bertos/cpu/cortex-m3/io/sam3_usart.h | 4 +- bertos/cpu/cortex-m3/io/sam3_wdt.h | 2 +- bertos/cpu/cortex-m3/io/sam3n.h | 8 +- .../{at91sam3n4_ram.ld => sam3n4_ram.ld} | 4 +- .../{at91sam3n4_rom.ld => sam3n4_rom.ld} | 4 +- bertos/cpu/detect.h | 78 +++++++++---------- 28 files changed, 85 insertions(+), 85 deletions(-) rename bertos/cpu/cortex-m3/info/{AT91SAM3N4.cdef => SAM3N4.cdef} (95%) rename bertos/cpu/cortex-m3/scripts/{at91sam3n4_ram.ld => sam3n4_ram.ld} (94%) rename bertos/cpu/cortex-m3/scripts/{at91sam3n4_rom.ld => sam3n4_rom.ld} (94%) diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h index 8232091d..2dab957f 100644 --- a/bertos/cpu/attr.h +++ b/bertos/cpu/attr.h @@ -171,7 +171,7 @@ #define CPU_HARVARD 0 /// Valid pointers should be >= than this value (used for debug) - #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_AT91SAM3) + #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_SAM3) #define CPU_RAM_START 0x20000000 #else #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000 diff --git a/bertos/cpu/cortex-m3/drv/clock_cm3.h b/bertos/cpu/cortex-m3/drv/clock_cm3.h index 0479f902..6353c6ab 100644 --- a/bertos/cpu/cortex-m3/drv/clock_cm3.h +++ b/bertos/cpu/cortex-m3/drv/clock_cm3.h @@ -42,7 +42,7 @@ #include "clock_lm3s.h" #elif CPU_CM3_STM32 #include "clock_stm32.h" -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include "clock_sam3.h" /*#elif Add other Cortex-M3 CPUs here */ #else diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c index 6df20451..55173e62 100644 --- a/bertos/cpu/cortex-m3/drv/clock_sam3.c +++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c @@ -30,7 +30,7 @@ * * --> * - * \brief ATSAM3 clock setup. + * \brief Atmel SAM3 clock setup. * * \author Stefano Fedrigo */ diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.h b/bertos/cpu/cortex-m3/drv/clock_sam3.h index 82af6547..88f21a2c 100644 --- a/bertos/cpu/cortex-m3/drv/clock_sam3.h +++ b/bertos/cpu/cortex-m3/drv/clock_sam3.h @@ -30,14 +30,14 @@ * * --> * - * \brief Low-level clocking driver for AT91SAM3. + * \brief Low-level clocking driver for SAM3. * * \author Stefano Fedrigo */ -#ifndef DRV_AT91SAM3_CLOCK_H -#define DRV_AT91SAM3_CLOCK_H +#ifndef DRV_SAM3_CLOCK_H +#define DRV_SAM3_CLOCK_H void clock_init(void); -#endif /* DRV_AT91SAM3_CLOCK_H */ +#endif /* DRV_SAM3_CLOCK_H */ diff --git a/bertos/cpu/cortex-m3/drv/irq_cm3.h b/bertos/cpu/cortex-m3/drv/irq_cm3.h index 93a75f53..84981839 100644 --- a/bertos/cpu/cortex-m3/drv/irq_cm3.h +++ b/bertos/cpu/cortex-m3/drv/irq_cm3.h @@ -44,7 +44,7 @@ #include #elif CPU_CM3_STM32 #include -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include /*#elif Add other families here */ #else diff --git a/bertos/cpu/cortex-m3/drv/kdebug_cm3.c b/bertos/cpu/cortex-m3/drv/kdebug_cm3.c index d3b5409d..ea592375 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_cm3.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_cm3.c @@ -41,7 +41,7 @@ #include "kdebug_lm3s.c" #elif CPU_CM3_STM32 #include "kdebug_stm32.c" -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include "kdebug_sam3.c" /*#elif Add other families here */ #else diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c index 9cfe143f..3438c05c 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c @@ -30,7 +30,7 @@ * * --> * - * \brief AT91SAM3 debug support (implementation). + * \brief SAM3 debug support (implementation). * * \author Stefano Fedrigo */ @@ -46,7 +46,7 @@ #define UART_ID UART0_ID #define UART_PIO_BASE PIOA_BASE #define UART_PINS (BV(RXD0) | BV(TXD0)) -#elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_AT91SAM3U) +#elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_SAM3U) #define UART_BASE UART1_BASE #define UART_ID UART1_ID #define UART_PIO_BASE PIOB_BASE diff --git a/bertos/cpu/cortex-m3/drv/ser_cm3.h b/bertos/cpu/cortex-m3/drv/ser_cm3.h index 184846bd..ddc78bec 100644 --- a/bertos/cpu/cortex-m3/drv/ser_cm3.h +++ b/bertos/cpu/cortex-m3/drv/ser_cm3.h @@ -41,7 +41,7 @@ #include "ser_lm3s.h" #elif CPU_CM3_STM32 #include "ser_stm32.h" -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include "ser_sam3.h" /*#elif Add other Cortex-M3 CPUs here */ #else diff --git a/bertos/cpu/cortex-m3/drv/ser_sam3.c b/bertos/cpu/cortex-m3/drv/ser_sam3.c index 0c5f8c39..b6f6eae5 100644 --- a/bertos/cpu/cortex-m3/drv/ser_sam3.c +++ b/bertos/cpu/cortex-m3/drv/ser_sam3.c @@ -119,7 +119,7 @@ /* End USART0 macros */ -#if !CPU_CM3_AT91SAM3U +#if !CPU_CM3_SAM3U #ifndef SER_UART1_BUS_TXINIT /** @@ -134,7 +134,7 @@ #define SER_UART1_BUS_TXINIT do { \ PIOA_PDR = BV(RXD1) | BV(TXD1); \ } while (0) - #elif CPU_CM3_AT91SAM3 + #elif CPU_CM3_SAM3 #define SER_UART1_BUS_TXINIT do { \ PIOB_PDR = BV(RXD1) | BV(TXD1); \ } while (0) @@ -182,7 +182,7 @@ * Default TXINIT macro - invoked in spi_init() * The default is no action. */ - #if CPU_CM3_AT91SAM3 + #if CPU_CM3_SAM3 #define SER_SPI0_BUS_TXINIT do { \ /* Disable PIO on SPI pins */ \ PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \ @@ -279,7 +279,7 @@ INLINE void sysirq_setPriority(sysirq_t irq, int prio) AIC_EOICR = 0; \ } while (0) -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 /** Inform hw that we have served the IRQ */ #define SER_INT_ACK do { /* nop */ } while (0) @@ -296,7 +296,7 @@ extern struct Serial *ser_handles[SER_CNT]; /* TX and RX buffers */ static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; -#if !CPU_CM3_AT91SAM3U +#if !CPU_CM3_SAM3U static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; #endif @@ -330,7 +330,7 @@ struct ArmSerial }; static ISR_PROTO(uart0_irq_dispatcher); -#if !CPU_CM3_AT91SAM3U +#if !CPU_CM3_SAM3U static ISR_PROTO(uart1_irq_dispatcher); #endif static ISR_PROTO(spi0_irq_handler); diff --git a/bertos/cpu/cortex-m3/drv/ser_sam3.h b/bertos/cpu/cortex-m3/drv/ser_sam3.h index ed294245..e1e0d9ee 100644 --- a/bertos/cpu/cortex-m3/drv/ser_sam3.h +++ b/bertos/cpu/cortex-m3/drv/ser_sam3.h @@ -70,7 +70,7 @@ typedef uint32_t serstatus_t; enum { SER_UART0, -#if !CPU_CM3_AT91SAM3U +#if !CPU_CM3_SAM3U SER_UART1, #endif SER_SPI0, diff --git a/bertos/cpu/cortex-m3/drv/timer_cm3.h b/bertos/cpu/cortex-m3/drv/timer_cm3.h index 80ec8eb7..0d45ad26 100644 --- a/bertos/cpu/cortex-m3/drv/timer_cm3.h +++ b/bertos/cpu/cortex-m3/drv/timer_cm3.h @@ -47,7 +47,7 @@ #include #elif CPU_CM3_STM32 #include -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include /*#elif Add other families here */ #else diff --git a/bertos/cpu/cortex-m3/info/AT91SAM3N4.cdef b/bertos/cpu/cortex-m3/info/SAM3N4.cdef similarity index 95% rename from bertos/cpu/cortex-m3/info/AT91SAM3N4.cdef rename to bertos/cpu/cortex-m3/info/SAM3N4.cdef index 9afa0e6d..22e136fd 100644 --- a/bertos/cpu/cortex-m3/info/AT91SAM3N4.cdef +++ b/bertos/cpu/cortex-m3/info/SAM3N4.cdef @@ -61,5 +61,5 @@ CPU_DESC += [ "256 Kbytes on-chip flash memory", "24 Kbytes on-chip SRAM memory" ] # GCC flags for this cpu. -MK_CPU_CPPFLAGS += " -D__ARM_AT91SAM3N4__" -MK_CPU_LDFLAGS += " -T " + SCRIPT_DIR + "at91sam3n4_ram.ld" +MK_CPU_CPPFLAGS += " -D__ARM_SAM3N4__" +MK_CPU_LDFLAGS += " -T " + SCRIPT_DIR + "sam3n4_ram.ld" diff --git a/bertos/cpu/cortex-m3/io/cm3.h b/bertos/cpu/cortex-m3/io/cm3.h index e3829958..8d1b4153 100644 --- a/bertos/cpu/cortex-m3/io/cm3.h +++ b/bertos/cpu/cortex-m3/io/cm3.h @@ -42,7 +42,7 @@ #include "lm3s.h" #elif CPU_CM3_STM32 #include "stm32.h" -#elif CPU_CM3_AT91SAM3 +#elif CPU_CM3_SAM3 #include "sam3.h" /*#elif Add other Cortex-M3 CPUs here */ #else diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h index 8b990550..2b58220d 100644 --- a/bertos/cpu/cortex-m3/io/sam3.h +++ b/bertos/cpu/cortex-m3/io/sam3.h @@ -43,7 +43,7 @@ * Peripherals IDs. */ /*\{*/ -#if CPU_CM3_AT91SAM3N +#if CPU_CM3_SAM3N #define SUPC_ID 0 ///< Supply Controller (SUPC) #define RSTC_ID 1 ///< Reset Controller (RSTC) #define RTC_ID 2 ///< Real Time Clock (RTC) @@ -114,7 +114,7 @@ * UART I/O pins */ /*\{*/ -#if CPU_CM3_AT91SAM3U +#if CPU_CM3_SAM3U #define RXD0 11 #define TXD0 12 #else @@ -129,7 +129,7 @@ * PIO I/O pins */ /*\{*/ -#if CPU_CM3_AT91SAM3U +#if CPU_CM3_SAM3U #define SPI0_SPCK 15 #define SPI0_MOSI 14 #define SPI0_MISO 13 diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h index 74257a8d..17b5be5e 100644 --- a/bertos/cpu/cortex-m3/io/sam3_flash.h +++ b/bertos/cpu/cortex-m3/io/sam3_flash.h @@ -30,7 +30,7 @@ * * --> * - * \brief ATSAM3 enhanced embedded flash controller definitions. + * \brief Atmel SAM3 enhanced embedded flash controller definitions. */ #ifndef SAM3_FLASH_H diff --git a/bertos/cpu/cortex-m3/io/sam3_ints.h b/bertos/cpu/cortex-m3/io/sam3_ints.h index 88fc69f6..4005ffe0 100644 --- a/bertos/cpu/cortex-m3/io/sam3_ints.h +++ b/bertos/cpu/cortex-m3/io/sam3_ints.h @@ -30,7 +30,7 @@ * * --> * - * \brief AT91SAM3 interrupt definitions. + * \brief SAM3 interrupt definitions. */ #ifndef SAM3_INTS_H diff --git a/bertos/cpu/cortex-m3/io/sam3_nvic.h b/bertos/cpu/cortex-m3/io/sam3_nvic.h index 0b3538c9..7b8d6eab 100644 --- a/bertos/cpu/cortex-m3/io/sam3_nvic.h +++ b/bertos/cpu/cortex-m3/io/sam3_nvic.h @@ -30,7 +30,7 @@ * * --> * - * \brief ATSAM3 NVIC hardware. + * \brief Atmel SAM3 NVIC hardware. * * This file does not follow the BeRTOS AT91 register naming convention, * because the NVIC subsystem is in common with other Cortex-M3 ports. diff --git a/bertos/cpu/cortex-m3/io/sam3_pio.h b/bertos/cpu/cortex-m3/io/sam3_pio.h index a8c35df5..443b873c 100644 --- a/bertos/cpu/cortex-m3/io/sam3_pio.h +++ b/bertos/cpu/cortex-m3/io/sam3_pio.h @@ -33,7 +33,7 @@ * * \author Francesco Sacchi * - * ATSAM3 Parallel input/output controller. + * Atmel SAM3 Parallel input/output controller. * This file is based on NUT/OS implementation. See license below. */ diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h index b44a3f50..b661c3b9 100644 --- a/bertos/cpu/cortex-m3/io/sam3_pmc.h +++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h @@ -30,7 +30,7 @@ * * --> * - * \brief AT91SAM3 PMC hardware. + * \brief SAM3 PMC hardware. */ #ifndef SAM3_PMC_H diff --git a/bertos/cpu/cortex-m3/io/sam3_spi.h b/bertos/cpu/cortex-m3/io/sam3_spi.h index 97859959..7024365b 100644 --- a/bertos/cpu/cortex-m3/io/sam3_spi.h +++ b/bertos/cpu/cortex-m3/io/sam3_spi.h @@ -33,7 +33,7 @@ * * \author Francesco Sacchi * - * ATSAM3 SPI register definitions. + * Atmel SAM3 SPI register definitions. * This file is based on NUT/OS implementation. See license below. */ diff --git a/bertos/cpu/cortex-m3/io/sam3_sysctl.h b/bertos/cpu/cortex-m3/io/sam3_sysctl.h index e1ccb534..f83cce21 100644 --- a/bertos/cpu/cortex-m3/io/sam3_sysctl.h +++ b/bertos/cpu/cortex-m3/io/sam3_sysctl.h @@ -30,7 +30,7 @@ * * --> * - * \brief ATSAM3 system controller registers. + * \brief Atmel SAM3 system controller registers. */ #ifndef SAM3_SYSCTL_H diff --git a/bertos/cpu/cortex-m3/io/sam3_uart.h b/bertos/cpu/cortex-m3/io/sam3_uart.h index 6dbcf15f..9a4e12b5 100644 --- a/bertos/cpu/cortex-m3/io/sam3_uart.h +++ b/bertos/cpu/cortex-m3/io/sam3_uart.h @@ -30,7 +30,7 @@ * * --> * - * \brief AT91SAM3 UART hardware. + * \brief SAM3 UART hardware. */ #ifndef SAM3_UART_H @@ -41,7 +41,7 @@ */ /*\{*/ #define UART0_BASE 0x400E0600 -#ifndef CPU_CM3_AT91SAM3U +#ifndef CPU_CM3_SAM3U #define UART1_BASE 0x400E0800 #endif /*\}*/ diff --git a/bertos/cpu/cortex-m3/io/sam3_usart.h b/bertos/cpu/cortex-m3/io/sam3_usart.h index f5c05c1c..405c0890 100644 --- a/bertos/cpu/cortex-m3/io/sam3_usart.h +++ b/bertos/cpu/cortex-m3/io/sam3_usart.h @@ -33,7 +33,7 @@ * * \author Daniele Basile * - * ATSAM3 USART User interface. + * Atmel SAM3 USART User interface. * This file is based on NUT/OS implementation. See license below. */ /* @@ -74,7 +74,7 @@ /** * USART base addresses. */ -#if CPU_CM3_AT91SAM3U +#if CPU_CM3_SAM3U #define USART0_BASE 0x40090000 #define USART1_BASE 0x40094000 #define USART2_BASE 0x40098000 diff --git a/bertos/cpu/cortex-m3/io/sam3_wdt.h b/bertos/cpu/cortex-m3/io/sam3_wdt.h index 833743a7..8c8325ca 100644 --- a/bertos/cpu/cortex-m3/io/sam3_wdt.h +++ b/bertos/cpu/cortex-m3/io/sam3_wdt.h @@ -32,7 +32,7 @@ * * \author Francesco Sacchi * - * ATSAM3 Watchdog. + * Atmel SAM3 Watchdog. * This file is based on NUT/OS implementation. See license below. */ diff --git a/bertos/cpu/cortex-m3/io/sam3n.h b/bertos/cpu/cortex-m3/io/sam3n.h index e0bc9f33..f962142d 100644 --- a/bertos/cpu/cortex-m3/io/sam3n.h +++ b/bertos/cpu/cortex-m3/io/sam3n.h @@ -30,7 +30,7 @@ * * --> * - * \brief Atmel's ATSAM3 registers definitions. + * \brief Atmel's SAM3 registers definitions. * * This file derives from the one included in Atmel softpack, and defines * registers not yet written in standard BeRTOS include file (io/sam3_*.h) with @@ -4316,21 +4316,21 @@ typedef struct { #define IROM_ADDR (0x00800000u) /* Internal ROM base address */ #define IRAM_ADDR (0x20000000u) /* Internal RAM base address */ -#if CPU_CM3_AT91SAM3N1 +#if CPU_CM3_SAM3N1 #define IFLASH_SIZE 0x10000 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ #define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */ #define IFLASH_NB_OF_LOCK_BITS (4) /* Internal FLASH 0 Number of Lock Bits: 4 */ #define IRAM_SIZE 0x2000 -#elif CPU_CM3_AT91SAM3N2 +#elif CPU_CM3_SAM3N2 #define IFLASH_SIZE 0x20000 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ #define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */ #define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */ #define IRAM_SIZE 0x4000 -#elif CPU_CM3_AT91SAM3N4 +#elif CPU_CM3_SAM3N4 #define IFLASH_SIZE 0x40000 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ diff --git a/bertos/cpu/cortex-m3/scripts/at91sam3n4_ram.ld b/bertos/cpu/cortex-m3/scripts/sam3n4_ram.ld similarity index 94% rename from bertos/cpu/cortex-m3/scripts/at91sam3n4_ram.ld rename to bertos/cpu/cortex-m3/scripts/sam3n4_ram.ld index e1b9257e..ad3bf375 100644 --- a/bertos/cpu/cortex-m3/scripts/at91sam3n4_ram.ld +++ b/bertos/cpu/cortex-m3/scripts/sam3n4_ram.ld @@ -32,12 +32,12 @@ * * \author Stefano Fedrigo * - * \brief Linker script for AT91SAM3N4 Cortex M3 processor. + * \brief Linker script for Atmel SAM3N4 Cortex M3 processor. * */ /* - * Memory configuration for AT91SAM3N4. + * Memory configuration for SAM3N4. */ MEMORY { diff --git a/bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld b/bertos/cpu/cortex-m3/scripts/sam3n4_rom.ld similarity index 94% rename from bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld rename to bertos/cpu/cortex-m3/scripts/sam3n4_rom.ld index 323f044a..170ff03b 100644 --- a/bertos/cpu/cortex-m3/scripts/at91sam3n4_rom.ld +++ b/bertos/cpu/cortex-m3/scripts/sam3n4_rom.ld @@ -32,12 +32,12 @@ * * \author Stefano Fedrigo * - * \brief Linker script for AT91SAM3N4 Cortex M3 processor. + * \brief Linker script for Atmel SAM3N4 Cortex M3 processor. * */ /* - * Memory configuration for AT91SAM3N4. + * Memory configuration for SAM3N4. */ MEMORY { diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index 985d18e1..7b57ae70 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -213,42 +213,42 @@ #define CPU_CM3_STM32F103RB 0 #endif - #if defined (__ARM_AT91SAM3N4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3N 1 - #define CPU_CM3_AT91SAM3N4 1 - #define CPU_NAME "AT91SAM3N4" - - #define CPU_CM3_AT91SAM3S 0 - #define CPU_CM3_AT91SAM3U 0 - #define CPU_CM3_AT91SAM3N2 0 - #define CPU_CM3_AT91SAM3N1 0 + #if defined (__ARM_SAM3N4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3N 1 + #define CPU_CM3_SAM3N4 1 + #define CPU_NAME "SAM3N4" + + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3U 0 + #define CPU_CM3_SAM3N2 0 + #define CPU_CM3_SAM3N1 0 #else - #define CPU_CM3_AT91SAM3N4 0 + #define CPU_CM3_SAM3N4 0 #endif - #if defined (__ARM_AT91SAM3S4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3S 1 - #define CPU_CM3_AT91SAM3S4 1 - #define CPU_NAME "AT91SAM3S4" + #if defined (__ARM_SAM3S4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3S 1 + #define CPU_CM3_SAM3S4 1 + #define CPU_NAME "SAM3S4" - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3U 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3U 0 #else - #define CPU_CM3_AT91SAM3S4 0 + #define CPU_CM3_SAM3S4 0 #endif - #if defined (__ARM_AT91SAM3U4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3U 1 - #define CPU_CM3_AT91SAM3U4 1 - #define CPU_NAME "AT91SAM3U4" + #if defined (__ARM_SAM3U4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3U 1 + #define CPU_CM3_SAM3U4 1 + #define CPU_NAME "SAM3U4" - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3S 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3S 0 #else - #define CPU_CM3_AT91SAM3U4 0 + #define CPU_CM3_SAM3U4 0 #endif #if defined (CPU_CM3_LM3S) @@ -256,19 +256,19 @@ #error Luminary Cortex-M3 CPU configuration error #endif #define CPU_CM3_STM32 0 - #define CPU_CM3_AT91SAM3 0 + #define CPU_CM3_SAM3 0 #elif defined (CPU_CM3_STM32) #if CPU_CM3_STM32F103RB + 0 != 1 #error STM32 Cortex-M3 CPU configuration error #endif #define CPU_CM3_LM3S 0 - #define CPU_CM3_AT91SAM3 0 - #elif defined (CPU_CM3_AT91SAM3) - #if CPU_CM3_AT91SAM3N + 0 != 1 - #error AT91SAM3 Cortex-M3 CPU configuration error + #define CPU_CM3_SAM3 0 + #elif defined (CPU_CM3_SAM3) + #if CPU_CM3_SAM3N + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error #endif - #if CPU_CM3_AT91SAM3N4 + CPU_CM3_AT91SAM3S4 + CPU_CM3_AT91SAM3U4 + 0 != 1 - #error AT91SAM3 Cortex-M3 CPU configuration error + #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error #endif #define CPU_CM3_LM3S 0 #define CPU_CM3_STM32 0 @@ -276,11 +276,11 @@ #else #define CPU_CM3_LM3S 0 #define CPU_CM3_STM32 0 - #define CPU_CM3_AT91SAM3 0 + #define CPU_CM3_SAM3 0 #endif - #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_AT91SAM3 + 0 /* Add other Cortex-M3 families here */ != 1 + #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1 #error Cortex-M3 CPU configuration error #endif @@ -293,9 +293,9 @@ #define CPU_CM3_STM32 0 #define CPU_CM3_STM32F103RB 0 - #define CPU_CM3_AT91SAM3 0 - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3N4 0 + #define CPU_CM3_SAM3 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3N4 0 #endif #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \ -- 2.25.1